74VCX16835MTDX

74VCX16835MTDX Datasheet

74VCX16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs

Part	Datasheet
74VCX16835MTDX	74VCX16835MTDX (pdf)

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74VCX16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs 74VCX16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs The VCX16835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow is controlled by output-enable OE , latch-enable LE , and clock CLK inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs In to Ouputs On a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state. The 74VCX16835 is designed for low voltage 1.65V to 3.6V VCC applications with I/O capability up to 3.6V. The 74VCX16835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s Compatible with PC100 DIMM module specifications s VCC supply operation s 3.6V tolerant inputs and outputs s tPD CLK to On 4.2ns max for 3.0V to 3.6V VCC 5.2ns max for 2.3V to 2.7V VCC 9.2ns max for 1.65V to 1.95V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s Static Drive IOH/IOL ±24mA 3.0V ±18mA 2.3V ±6mA 1.65V s Latchup performance exceeds 300 mA s ESD performance: Human body model > 2000V Machine model >200V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Preliminary Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC OE to GND through a pulldown resistor the minimum value of the resistor is determined by the current sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74VCX16835GX Note 2 BGA54A Preliminary 54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 74VCX16835MTD Note 3 MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Note 2 BGA package available in Tape and Reel only. Note 3 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2001 Fairchild Semiconductor Corporation DS500173 74VCX16835 Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA Top Thru View Pin Descriptions Pin Names OE LE CLK I1 - I18 O1 - O18 NC Output Enable Input Active LOW Latch Enable Input Clock Input Data Inputs 3-STATE Outputs No Connect FBGA Pin Assignments NC GND I1 O7 GND I7 O10 O9 GND I9 O12 O11 GND I11 O14 O13 VCC O16 O15 OE CLK I15 O17 O18 LE GND I18 Truth Table Inputs Outputs O0 Note 4 O0 Note 5 H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance = LOW-to-HIGH Clock Transition Note 4 Output level before the indicated steady-state input conditions were established provided that CLK was HIGH before LE went LOW. Note 5 Output level before the indicated steady-state input conditions were established. 74VCX16835 Logic Diagram 74VCX16835 Absolute Maximum Ratings Note 6 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Outputs 3-STATE Outputs Active Note 7 DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK VO < 0V VO > VCC DC Output Source/Sink Current IOH/IOL DC VCC or Ground Current per Supply Pin ICC or Ground Storage Temperature Range TSTG −0.5V to +4.6V −0.5V to +4.6V −0.5V to +4.6V to VCC + 0.5V −50 mA −50 mA +50 mA

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74VCX16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs
74VCX16835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs and Outputs

The VCX16835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.

Data flow is controlled by output-enable OE , latch-enable LE , and clock CLK inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs In to Ouputs On a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state.

The 74VCX16835 is designed for low voltage 1.65V to 3.6V VCC applications with I/O capability up to 3.6V.

The 74VCX16835 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s Compatible with PC100 DIMM module specifications s VCC supply operation s 3.6V tolerant inputs and outputs
s tPD CLK to On 4.2ns max for 3.0V to 3.6V VCC 5.2ns max for 2.3V to 2.7V VCC 9.2ns max for 1.65V to 1.95V VCC
s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1
s Static Drive IOH/IOL ±24mA 3.0V ±18mA 2.3V ±6mA 1.65V
s Latchup performance exceeds 300 mA
s ESD performance:

Human body model > 2000V Machine model >200V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Preliminary

Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC OE to GND through a pulldown resistor the minimum value of the resistor is determined by the current sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Description
74VCX16835GX Note 2

BGA54A Preliminary
54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide [TAPE and REEL]
74VCX16835MTD Note 3

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Note 2 BGA package available in Tape and Reel only. Note 3 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2001 Fairchild Semiconductor Corporation DS500173
74VCX16835

Connection Diagrams

Pin Assignment for TSSOP

Pin Assignment for FBGA Top Thru View

Pin Descriptions

Pin Names

OE LE CLK I1 - I18 O1 - O18 NC

Output Enable Input Active LOW Latch Enable Input Clock Input Data Inputs 3-STATE Outputs No Connect

FBGA Pin Assignments

NC GND I1

O7 GND I7

O10 O9 GND I9

O12 O11 GND I11

O14 O13 VCC

O16 O15 OE CLK I15

O17 O18 LE GND I18

Truth Table

Inputs

Outputs

O0 Note 4

O0 Note 5

H = Logic HIGH L = Logic LOW X = Don’t Care, but not floating Z = High Impedance = LOW-to-HIGH Clock Transition

Note 4 Output level before the indicated steady-state input conditions were established provided that CLK was HIGH before LE went LOW.

Note 5 Output level before the indicated steady-state input conditions were established.
74VCX16835

Logic Diagram
74VCX16835

Absolute Maximum Ratings Note 6

Supply Voltage VCC DC Input Voltage VI Output Voltage VO

Outputs 3-STATE

Outputs Active Note 7

DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK

VO < 0V VO > VCC DC Output Source/Sink Current

IOH/IOL DC VCC or Ground Current per

Supply Pin ICC or Ground Storage Temperature Range TSTG
−0.5V to +4.6V −0.5V to +4.6V
−0.5V to +4.6V to VCC + 0.5V
−50 mA
−50 mA +50 mA

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Datasheet ID: 74VCX16835MTDX 513468