74LVTH32245G

74LVTH32245G Datasheet

74LVT32245<br>• 74LVTH32245 Low Voltage 32-Bit Transceiver with 3-STATE Outputs

Part	Datasheet
74LVTH32245G	74LVTH32245G (pdf)

Related Parts	Information
74LVTH32245GX	74LVTH32245GX

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74LVT32245 • 74LVTH32245 Low Voltage 32-Bit Transceiver with 3-STATE Outputs 74LVT32245 • 74LVTH32245 Low Voltage 32-Bit Transceiver with 3-STATE Outputs The LVT32245 and LVTH32245 contain thirty-two noninverting bidirectional buffers with 3-STATE outputs and are intended for bus oriented applications. The devices are byte controlled. Each byte has separate control inputs which can be shorted together for full 32-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state. The LVTH32245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These non-inverting transceivers are designed for low voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT32245 and LVTH32245 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH32245 , also available without bushold feature 74LVT32245 . s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink −32 mA/+64 mA s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V s Packaged in plastic Fine-Pitch Ball Grid Array FBGA Ordering Code: Order Number Package Number Package Description 74LVT32245G Note 1 Note 2 BGA96A 96-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide 74LVTH32245G Note 1 Note 2 BGA96A 96-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide Note 1 Ordering code “G” indicates Trays. Note 2 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol 2002 Fairchild Semiconductor Corporation DS500433 74LVT32245 • 74LVTH32245 Connection Diagram Top Thru View Truth Tables Inputs T/R1 Inputs T/R2 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance Outputs Bus Data to Bus Data to Bus State on Outputs Bus Data to Bus Data to Bus State on Pin Descriptions Pin Names OEn T/Rn Output Enable Input Active LOW Transmit/Receive Input Side A Inputs/3-STATE Outputs Side B Inputs/3-STATE Outputs FBGA Pin Assignments B0 T/R1 OE1 A0 B2 GND A2 B4 VCC1 A4 B6 GND A6 B8 GND A8 B10 VCC1 A10 B13 B12 GND A12 A13 B14 B15 T/R2 OE2 A15 A14 B17 B16 T/R3 OE3 A16 A17 B19 B18 GND A18 A19 B21 B20 VCC2 A20 A21 B23 B22 GND A22 A23 B25 B24 GND A24 A25 B27 B26 VCC2 A26 A27 B29 B28 GND A28 A29 B30 B31 T/R4 OE4 A31 A30 Inputs T/R3 Outputs Bus Data to Bus Data to Bus State on

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74LVT32245
• 74LVTH32245 Low Voltage 32-Bit Transceiver with 3-STATE Outputs
74LVT32245
• 74LVTH32245 Low Voltage 32-Bit Transceiver with 3-STATE Outputs

The LVT32245 and LVTH32245 contain thirty-two noninverting bidirectional buffers with 3-STATE outputs and are intended for bus oriented applications. The devices are byte controlled. Each byte has separate control inputs which can be shorted together for full 32-bit operation. The T/R inputs determine the direction of data flow through the device. The OE inputs disable both the A and B ports by placing them in a high impedance state.

The LVTH32245 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

These non-inverting transceivers are designed for low voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT32245 and LVTH32245 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
s Input and output interface capability to systems at 5V VCC
s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH32245 , also available without bushold feature 74LVT32245 .
s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free
bus loading s Outputs source/sink −32 mA/+64 mA s ESD performance:

Human-body model > 2000V Machine model > 200V Charged-device model > 1000V s Packaged in plastic Fine-Pitch Ball Grid Array FBGA
Ordering Code:

Order Number Package Number

Package Description
74LVT32245G Note 1 Note 2

BGA96A
96-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide
74LVTH32245G Note 1 Note 2

BGA96A
96-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide
Note 1 Ordering code “G” indicates Trays.
Note 2 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol
2002 Fairchild Semiconductor Corporation DS500433
74LVT32245
• 74LVTH32245

Connection Diagram

Top Thru View

Truth Tables

Inputs

T/R1

Inputs

T/R2

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance

Outputs

Bus Data to Bus Data to Bus State on

Outputs

Bus Data to Bus Data to Bus State on

Pin Descriptions

Pin Names

OEn T/Rn

Output Enable Input Active LOW Transmit/Receive Input Side A Inputs/3-STATE Outputs Side B Inputs/3-STATE Outputs

FBGA Pin Assignments

B0 T/R1 OE1 A0

B2 GND A2

B4 VCC1 A4

B6 GND A6

B8 GND A8

B10 VCC1 A10

B13 B12 GND A12 A13

B14 B15 T/R2 OE2 A15 A14

B17 B16 T/R3 OE3 A16 A17

B19 B18 GND A18 A19

B21 B20 VCC2 A20 A21

B23 B22 GND A22 A23

B25 B24 GND A24 A25

B27 B26 VCC2 A26 A27

B29 B28 GND A28 A29

B30 B31 T/R4 OE4 A31 A30

Inputs

T/R3

Outputs

Bus Data to Bus Data to Bus State on

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Datasheet ID: 74LVTH32245G 513438