74LVTH16835MEA

74LVTH16835MEA Datasheet

74LVTH16835 Low Voltage 18-Bit Universal Bus Driver

Part	Datasheet
74LVTH16835MEA	74LVTH16835MEA (pdf)

Related Parts	Information
74LVTH16835MTD	74LVTH16835MTD
74LVTH16835MEAX	74LVTH16835MEAX
74LVTH16835MTDX	74LVTH16835MTDX

PDF Datasheet Preview
74LVTH16835 Low Voltage 18-Bit Universal Bus Driver 74LVTH16835 Low Voltage 18-Bit Universal Bus Driver with Bushold and 3-STATE Outputs The LVTH16835 is an 18-bit universal bus driver that combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow is controlled by output-enable OE , latch-enable LE , and clock CLK inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs An to Outputs Yn on a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state. The LVTH16835 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. The bus driver is designed for low voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH16835 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs s Live insertion/extraction permitted s Power up/down high impedance provides glitch-free bus loading s Outputs source/sink −32 mA/+64 mA s ESD Performance: Human-Body Model > 2000V Machine Model > 200V Charged-Device Model > 1000V Ordering Code: Order Number Package Number Package Description 74LVTH16835MEA MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide 74LVTH16835MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2001 Fairchild Semiconductor Corporation DS500102 74LVTH16835 Connection Diagram Pin Descriptions Pin Names CLK OE LE Description Data Register Inputs 3-STATE Outputs Clock Pulse Input Output Enable Input Latch Enable Input Function Table Inputs Output Y0 Note 1 Y0 Note 2 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance = HIGH-to-LOW Clock Transition Note 1 Output level before the indicated steady-state input conditions were established, provided that CLK was HIGH before LE went LOW. Note 2 Output level before the indicated steady-state input conditions were established. Logic Diagram 74LVTH16835 Absolute Maximum Ratings Note 3 VCC VI VO Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current ICC IGND TSTG DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value to −50 −50 64 128 ±64 ±128 −65 to +150 Conditions Output in 3-STATE Output in HIGH or LOW State Note 4 VI < GND VO < GND VO > VCC Output at HIGH State VO > VCC Output at LOW State Units V mA mA °C Recommended Operating Conditions Parameter Units Supply Voltage Input Voltage HIGH-Level Output Current

PDF Datasheet Preview

74LVTH16835 Low Voltage 18-Bit Universal Bus Driver
74LVTH16835 Low Voltage 18-Bit Universal Bus Driver with Bushold and 3-STATE Outputs

The LVTH16835 is an 18-bit universal bus driver that combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.

Data flow is controlled by output-enable OE , latch-enable LE , and clock CLK inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs An to Outputs Yn on a Positive Edge Transition of the Clock. When OE is LOW, the output data is enabled. When OE is HIGH the output port is in a high impedance state.

The LVTH16835 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

The bus driver is designed for low voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVTH16835 is fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
s Input and output interface capability to systems at 5V VCC
s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs
s Live insertion/extraction permitted s Power up/down high impedance provides glitch-free bus
loading s Outputs source/sink −32 mA/+64 mA s ESD Performance:

Human-Body Model > 2000V Machine Model > 200V Charged-Device Model > 1000V
Ordering Code:

Order Number Package Number

Package Description
74LVTH16835MEA

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
74LVTH16835MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2001 Fairchild Semiconductor Corporation DS500102
74LVTH16835

Connection Diagram

Pin Descriptions

Pin Names CLK OE LE

Description Data Register Inputs 3-STATE Outputs Clock Pulse Input Output Enable Input Latch Enable Input

Function Table

Inputs

Output

Y0 Note 1

Y0 Note 2

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance
= HIGH-to-LOW Clock Transition

Note 1 Output level before the indicated steady-state input conditions were established, provided that CLK was HIGH before LE went LOW.

Note 2 Output level before the indicated steady-state input conditions were established.

Logic Diagram
74LVTH16835

Absolute Maximum Ratings Note 3

VCC VI VO

Parameter Supply Voltage DC Input Voltage DC Output Voltage

DC Input Diode Current

DC Output Diode Current

DC Output Current

ICC IGND TSTG

DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature

Value to
−50 −50 64 128 ±64 ±128 −65 to +150

Conditions

Output in 3-STATE Output in HIGH or LOW State Note 4 VI < GND VO < GND VO > VCC Output at HIGH State VO > VCC Output at LOW State

Units V mA
mA °C

Recommended Operating Conditions

Parameter

Units

Supply Voltage

Input Voltage

HIGH-Level Output Current

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 74LVTH16835MEA Datasheet file may be downloaded here without warranties.

Datasheet ID: 74LVTH16835MEA 513436