74LVTH16952MEAX

74LVTH16952MEAX Datasheet

74LVT16952<br>• 74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs

Part	Datasheet
74LVTH16952MEAX	74LVTH16952MEAX (pdf)

Related Parts	Information
74LVTH16952MTD	74LVTH16952MTD
74LVTH16952MTDX	74LVTH16952MTDX
74LVTH16952MEA	74LVTH16952MEA

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74LVT16952 • 74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs 74LVT16952 • 74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs The LVT16952 and LVTH16952 are 16-bit registered transceivers. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable, and output enable signals are provided for each register. The LVTH16952 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. The registered transceiver is designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16952 and LVTH16952 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation. s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH16952 s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink −32 mA/+64 mA s Functionally compatible with the 74 series 16952 s Latch-up conforms to JEDEC JED78 s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V Ordering Code: Order Number Package Number Package Description 74LVT16952MEA Preliminary MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide 74LVT16952MTD Preliminary MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide 74LVTH16952MEA MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide 74LVTH16952MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2001 Fairchild Semiconductor Corporation DS500103 74LVT16952 • 74LVTH16952 Connection Diagram Pin Descriptions Pin Names CPABn, CPBAn CEAn, CEBn OEABn, OEBAn Truth Table Note 1 Data Register A Inputs B-Register 3-STATE Outputs Data Register B Inputs A-Register 3-STATE Outputs Clock Pulse Inputs Clock Enable Output Enable Inputs Inputs Internal Register Output An CPABn CEAn OEABn Value H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = Output High Impedance = LOW-to-HIGH Transition. NC = No Change state established by last valid CP B0 = State established by last valid CP Note 1 A to B data flow shown B to A flow control is the same, but used OEBAn, CPBAn and CEBn. 74LVT16952 • 74LVTH16952 Logic Diagram Note n for either byte 1 or byte Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74LVT16952 • 74LVTH16952 Absolute Maximum Ratings Note 2 Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current ICC IGND TSTG DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value to −50 −50 64 128 ±64 ±128 −65 to +150 Conditions Output in 3-STATE Output in HIGH or LOW State Note 3 VI < GND VO < GND VO > VCC Output at HIGH State VO > VCC Output at LOW State Units V mA mA °C

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74LVT16952
• 74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs
74LVT16952
• 74LVTH16952 Low Voltage 16-Bit Registered Transceiver with 3-STATE Outputs

The LVT16952 and LVTH16952 are 16-bit registered transceivers. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable, and output enable signals are provided for each register.

The LVTH16952 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

The registered transceiver is designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment.

The LVT16952 and LVTH16952 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining low power dissipation.
s Input and output interface capability to systems at 5V VCC
s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH16952
s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free
bus loading s Outputs source/sink −32 mA/+64 mA s Functionally compatible with the 74 series 16952 s Latch-up conforms to JEDEC JED78 s ESD performance:

Human-body model > 2000V Machine model > 200V Charged-device model > 1000V
Ordering Code:

Order Number Package Number

Package Description
74LVT16952MEA Preliminary

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
74LVT16952MTD Preliminary

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
74LVTH16952MEA

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
74LVTH16952MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2001 Fairchild Semiconductor Corporation DS500103
74LVT16952
• 74LVTH16952

Connection Diagram

Pin Descriptions

Pin Names

CPABn, CPBAn CEAn, CEBn OEABn, OEBAn

Truth Table

Note 1

Data Register A Inputs B-Register 3-STATE Outputs

Data Register B Inputs A-Register 3-STATE Outputs

Clock Pulse Inputs

Clock Enable

Output Enable Inputs

Inputs

Internal Register Output

An CPABn CEAn OEABn

Value

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= Output High Impedance = LOW-to-HIGH Transition. NC = No Change state established by last valid CP B0 = State established by last valid CP

Note 1 A to B data flow shown B to A flow control is the same, but used OEBAn, CPBAn and CEBn.
74LVT16952
• 74LVTH16952

Logic Diagram

Note n for either byte 1 or byte Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74LVT16952
• 74LVTH16952

Absolute Maximum Ratings Note 2

Parameter

Supply Voltage

DC Input Voltage

DC Output Voltage

DC Input Diode Current

DC Output Diode Current

DC Output Current

ICC IGND TSTG

DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature

Value to
−50 −50 64 128 ±64 ±128 −65 to +150

Conditions

Output in 3-STATE Output in HIGH or LOW State Note 3 VI < GND VO < GND VO > VCC Output at HIGH State VO > VCC Output at LOW State

Units V mA
mA °C

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Datasheet ID: 74LVTH16952MEAX 513424