74LVT162240MTD

74LVT162240MTD Datasheet

74LVT162240<br>• 74LVTH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25 Series Resistors in the Outputs

Part	Datasheet
74LVT162240MTD	74LVT162240MTD (pdf)

Related Parts	Information
74LVTH162240MTX	74LVTH162240MTX
74LVTH162240MTD	74LVTH162240MTD
74LVT162240MEA	74LVT162240MEA
74LVTH162240MEX	74LVTH162240MEX
74LVT162240MTDX	74LVT162240MTDX
74LVT162240MEAX	74LVT162240MEAX
74LVTH162240MEA	74LVTH162240MEA

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74LVT162240 • 74LVTH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25 Series Resistors in the Outputs 74LVT162240 • 74LVTH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25 Series Resistors in the Outputs The LVT162240 and LVTH162240 contain sixteen inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Individual 3-STATE control inputs can be shorted together for 8-bit or 16-bit operation. The LVT162240 and LVTH162240 are designed with equivalent 25 series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters. The LVTH162240 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These inverting buffers and line drivers are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT162240 and LVTH162240 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation. s Input and output interface capability to systems at 5V VCC s Outputs include equivalent series resistance of 25 to make external termination resistors unnecessary and reduce overshoot and undershoot s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH162240 , also available without bushold feature 74LVT162240 s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Functionally compatible with the 74 series 162240 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V Ordering Code: Order Number Package Number Package Description 74LVT162240MEA Note 1 MS48A 48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide 74LVT162240MTD Note 1 MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide 74LVTH162240MEA MS48A 48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide [TUBE] 74LVTH162240MEX Note 2 MS48A 48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide [TAPE and REEL] 74LVTH162240MTD MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide [TUBE] 74LVTH162240MTX Note 2 MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide [TAPE and REEL] Note 1 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Note 2 Use this Order Number to receive devices in Tape and Reel. 2005 Fairchild Semiconductor Corporation DS012490 74LVT162240 • 74LVTH162240 Logic Symbol Pin Descriptions Connection Diagram Functional Description The LVT162240 and LVTH162240 contain sixteen inverting buffers with 3-STATE standard outputs. The device is nibble 4 bits controlled with each nibble functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The Logic Diagram Pin Names Output Enable Inputs Active LOW Inputs 3-STATE Outputs Truth Table Inputs Inputs Inputs Inputs OE4 L H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Outputs Outputs Outputs Outputs 3-STATE outputs are controlled by an Output Enable OEn input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74LVT162240 • 74LVTH162240 Absolute Maximum Ratings Note 3 VCC VI VO Parameter Supply Voltage DC Input Voltage Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current ICC IGND TSTG DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value to 128 r64 r128 to Recommended Operating Conditions Conditions Output in 3-STATE Output in HIGH or LOW State Note 4 VI GND VO GND VO ! VCC Output at HIGH State VO ! VCC Output at LOW State Units V mA qC Parameter

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74LVT162240
• 74LVTH162240 Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25 Series Resistors in the Outputs
74LVT162240
• 74LVTH162240

Low Voltage 16-Bit Inverting Buffer/Line Driver with 3-STATE Outputs and 25 Series Resistors in the Outputs

The LVT162240 and LVTH162240 contain sixteen inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Individual 3-STATE control inputs can be shorted together for 8-bit or 16-bit operation.

The LVT162240 and LVTH162240 are designed with equivalent 25 series resistance in both the HIGH and LOW states of the output. This design reduces line noise in applications such as memory address drivers, clock drivers, and bus transceivers/transmitters.

The LVTH162240 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

These inverting buffers and line drivers are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT162240 and LVTH162240 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation.
s Input and output interface capability to systems at 5V VCC
s Outputs include equivalent series resistance of 25 to make external termination resistors unnecessary and reduce overshoot and undershoot
s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH162240 , also available without bushold feature 74LVT162240
s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free
bus loading s Functionally compatible with the 74 series 162240 s Latch-up performance exceeds 500 mA s ESD performance:

Human-body model ! 2000V Machine model ! 200V Charged-device model ! 1000V
Ordering Code:

Order Number Package Number

Package Description
74LVT162240MEA Note 1

MS48A
48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide
74LVT162240MTD Note 1

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
74LVTH162240MEA

MS48A
48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide [TUBE]
74LVTH162240MEX Note 2

MS48A
48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide [TAPE and REEL]
74LVTH162240MTD

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide [TUBE]
74LVTH162240MTX Note 2

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide [TAPE and REEL]
Note 1 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Note 2 Use this Order Number to receive devices in Tape and Reel.
2005 Fairchild Semiconductor Corporation DS012490
74LVT162240
• 74LVTH162240

Logic Symbol

Pin Descriptions

Connection Diagram

Functional Description

The LVT162240 and LVTH162240 contain sixteen inverting buffers with 3-STATE standard outputs. The device is nibble 4 bits controlled with each nibble functioning identically, but independent of the other. The control pins may be shorted together to obtain full 16-bit operation. The

Logic Diagram

Pin Names

Output Enable Inputs Active LOW Inputs 3-STATE Outputs

Truth Table

Inputs

Inputs

Inputs

Inputs

OE4 L

H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance

Outputs

Outputs

Outputs

Outputs
3-STATE outputs are controlled by an Output Enable OEn input for each nibble. When OEn is LOW, the outputs are in 2-state mode. When OEn is HIGH, the outputs are in the high impedance mode, but this does not interfere with entering new data into the inputs.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74LVT162240
• 74LVTH162240

Absolute Maximum Ratings Note 3

VCC VI VO

Parameter Supply Voltage DC Input Voltage Output Voltage

DC Input Diode Current

DC Output Diode Current

DC Output Current

ICC IGND TSTG

DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature

Value to
128 r64 r128 to

Recommended Operating Conditions

Conditions

Output in 3-STATE Output in HIGH or LOW State Note 4 VI GND VO GND VO ! VCC Output at HIGH State VO ! VCC Output at LOW State

Units V
mA qC

Parameter

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Datasheet ID: 74LVT162240MTD 513422