74LVTH16244MTD

74LVTH16244MTD Datasheet

74LVT16244<br>• 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs

Part	Datasheet
74LVTH16244MTD	74LVTH16244MTD (pdf)

Related Parts	Information
74LVTH16244MTDX	74LVTH16244MTDX
74LVTH16244MEA	74LVTH16244MEA
74LVTH16244MEAX	74LVTH16244MEAX
74LVT16244MEAX	74LVT16244MEAX
74LVT16244MEA	74LVT16244MEA
74LVT16244MTD	74LVT16244MTD
74LVT16244MTDX	74LVT16244MTDX
74LVTH16244GX	74LVTH16244GX

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74LVT16244 • 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs 74LVT16244 • 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs The LVT16244 and LVTH16244 contain sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Individual 3-STATE control inputs can be shorted together for 8-bit or 16-bit operation. The LVTH16244 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These buffers and line drivers are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16244 and LVTH16244 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH16244 , also available without bushold feature 74LVT16244 . s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink mA s Functionally compatible with the 74 series 16244 s Latch-up performance exceeds 500 mA s ESD performance: Human-body model !2000V Machine model !200V Charged-drive model !1000V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Ordering Code: Order Number Package Number Package Description 74LVT16244G Note 1 Note 2 BGA54A 54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide 74LVT16244MEA Note 2 MS48A 48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide 74LVT16244MTD Note 2 MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide 74LVTH16244G Note 1 Note 2 BGA54A 54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide 74LVTH16244MEA Note 2 MS48A 48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide 74LVTH16244MTD Note 2 MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Note 1 Ordering code “G” indicates Trays. Note 2 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol 2005 Fairchild Semiconductor Corporation DS500151 74LVT16244 • 74LVTH16244 Connection Diagrams Pin Assignment for SSOP and TSSOP Pin Assignment for FBGA Top Thru View Logic Diagram Pin Descriptions Pin Names OEn NC Output Enable Inputs Active LOW Inputs Outputs No Connect FBGA Pin Assignments O0 NC OE1 OE2 NC O3 VCC O5 GND I5 O7 GND I7 O10 O9 GND I9 O11 VCC O14 O13 NC O15 NC OE4 OE3 NC Truth Table Inputs Inputs Inputs Inputs H High Voltage Level L Low Voltage Level X Immaterial Z High Impedance Outputs Outputs Outputs Outputs Functional Description The LVT16244 and LVTH16244 contain sixteen non-inverting buffers with 3-STATE outputs. The device is nibble 4-bits controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. 74LVT16244 • 74LVTH16244 Absolute Maximum Ratings Note 3 VCC VI VO Parameter Supply Voltage DC Input Voltage Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current ICC IGND TSTG

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74LVT16244
• 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs
74LVT16244
• 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs

The LVT16244 and LVTH16244 contain sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Individual 3-STATE control inputs can be shorted together for 8-bit or 16-bit operation.

The LVTH16244 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs.

These buffers and line drivers are designed for low-voltage 3.3V VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16244 and LVTH16244 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation
s Input and output interface capability to systems at 5V VCC
s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs 74LVTH16244 , also available without bushold feature 74LVT16244 .
s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free
bus loading s Outputs source/sink mA s Functionally compatible with the 74 series 16244 s Latch-up performance exceeds 500 mA s ESD performance:

Human-body model !2000V Machine model !200V Charged-drive model !1000V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA
Ordering Code:

Order Number

Package Number

Package Description
74LVT16244G Note 1 Note 2

BGA54A
54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide
74LVT16244MEA Note 2

MS48A
48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide
74LVT16244MTD Note 2

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
74LVTH16244G Note 1 Note 2

BGA54A
54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide
74LVTH16244MEA Note 2

MS48A
48-Lead Small Shrink Outline Package SSOP , JEDEC MO-118, Wide
74LVTH16244MTD Note 2

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Note 1 Ordering code “G” indicates Trays.
Note 2 Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol
2005 Fairchild Semiconductor Corporation DS500151
74LVT16244
• 74LVTH16244

Connection Diagrams

Pin Assignment for SSOP and TSSOP

Pin Assignment for FBGA Top Thru View

Logic Diagram

Pin Descriptions

Pin Names

OEn NC

Output Enable Inputs Active LOW Inputs Outputs No Connect

FBGA Pin Assignments

O0 NC OE1 OE2 NC

O3 VCC

O5 GND I5

O7 GND I7

O10 O9 GND I9

O11 VCC

O14 O13 NC

O15 NC OE4 OE3 NC

Truth Table

Inputs

Inputs

Inputs

Inputs

H High Voltage Level L Low Voltage Level X Immaterial Z High Impedance

Outputs

Outputs

Outputs

Outputs

Functional Description

The LVT16244 and LVTH16244 contain sixteen non-inverting buffers with 3-STATE outputs. The device is nibble 4-bits controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.
74LVT16244
• 74LVTH16244

Absolute Maximum Ratings Note 3

VCC VI VO

Parameter Supply Voltage DC Input Voltage Output Voltage

DC Input Diode Current

DC Output Diode Current

DC Output Current

ICC IGND TSTG

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Datasheet ID: 74LVTH16244MTD 513421