74LVQ74SJX

74LVQ74SJX Datasheet


74LVQ74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

Part Datasheet
74LVQ74SJX 74LVQ74SJX 74LVQ74SJX (pdf)
Related Parts Information
74LVQ74SJ 74LVQ74SJ 74LVQ74SJ
74LVQ74SCX 74LVQ74SCX 74LVQ74SCX
74LVQ74SC 74LVQ74SC 74LVQ74SC
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74LVQ74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop
74LVQ74 Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop

The LVQ74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.

Asynchronous Inputs:

LOW input to SD Set sets Q to HIGH level

LOW input to CD Clear sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on CD and SD makes both Q and Q HIGH
s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Guaranteed incident wave switching into
Ordering Code:

Order Number 74LVQ74SC 74LVQ74SJ

Package Number M14A M14D

Package Description 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names

D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2

Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs
2001 Fairchild Semiconductor Corporation DS011347
74LVQ74

Truth Table

Inputs

Outputs

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Clock Transition Q0 = Previous Q before LOW-to-HIGH Transition of Clock

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74LVQ74

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current

ICC or IGND Storage Temperature TSTG DC Latch-Up Source or

Sink Current
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
±50 mA
±200 mA −65°C to +150°C
±100 mA

Recommended Operating Conditions Note 2

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate

VIN from 0.8V to 2.0V VCC 3.0V
2.0V to 3.6V 0V to VCC 0V to VCC
−40°C to +85°C
125 mV/ns

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 2 Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Parameter

TA = +25°C
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Datasheet ID: 74LVQ74SJX 513419