74LVQ273SJ
74LVQ273SJ Datasheet
74LVQ273 Low Voltage Octal D-Type Flip-Flop
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74LVQ273SJ |
74LVQ273SJ (pdf) |
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74LVQ273SJX |
74LVQ273SJX |
74LVQ273QSCX |
74LVQ273QSCX |
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74LVQ273QSC |
74LVQ273QSC |
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74LVQ273SC |
74LVQ273SC |
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74LVQ273SCX |
74LVQ273SCX |
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| 74LVQ273 Low Voltage Octal D-Type Flip-Flop 74LVQ273 Low Voltage Octal D-Type Flip-Flop The LVQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP and Master Reset MR input load and reset clear all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. s Ideal for low power/low noise 3.3V applications s Implements patented EMI reduction circuitry s Available in SOIC JEDEC, SOIC EIAJ and QSOP packages s Guaranteed simultaneous switching noise level and dynamic threshold performance s Improved latch-up immunity s Guaranteed incident wave switching into s 4 kV minimum ESD immunity Ordering Code: Order Number Package Number Package Description 74LVQ273SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74LVQ273SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74LVQ273QSC MQA20 20-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names MR CP Description Data Inputs Master Reset Clock Pulse Input Data Outputs 2001 Fairchild Semiconductor Corporation DS011358 74LVQ273 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current ICC or IGND Storage Temperature TSTG DC Latch-up Source or Sink Current −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±400 mA −65°C to +150°C ±300 mA Recommended Operating Conditions Note 2 Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate VIN from 0.8V to 2.0V VCC 3.0V 2.0V to 3.6V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2 Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics Parameter TA = +25°C TA = −40°C to +85°C Units Guaranteed Limits Conditions Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage |
| More datasheets: 11807 RD005 | 11807 OR001 | 11807 GR005 | 11807 BR005 | 11807 BL001 | 11807 BL005 | 11807 BK001 | 11807 BK005 | 11807 OR005 | 74LVQ273SJX |
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