74LVQ240QSC

74LVQ240QSC Datasheet

74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

Part	Datasheet
74LVQ240QSC	74LVQ240QSC (pdf)

Related Parts	Information
74LVQ240SJX	74LVQ240SJX
74LVQ240SCX	74LVQ240SCX
74LVQ240SJ	74LVQ240SJ
74LVQ240QSCX	74LVQ240QSCX

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74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs 74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs The LVQ240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density. s Ideal for low power/low noise 3.3V applications s Implements patented EMI reduction circuitry s Available in SOIC JEDEC, SOIC EIAJ, and QSOP pack- ages s Guaranteed simultaneous switching noise level and dynamic threshold performance s Improved latch-up immunity s Guaranteed incident wave switching into s 4 kV minimum ESD immunity Ordering Code: Order Number Package Number Package Description 74LVQ240SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74LVQ240SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74LVQ240QSC MQA20 20-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions IEEE/IEC Pin Names OE1, OE2 Description 3-STATE Output Enable Inputs Outputs Truth Tables Connection Diagram Inputs Outputs Pins 12, 14, 16, 18 H L Z Inputs OE2 L H H = HIGH Voltage Level X = Immaterial Outputs Pins 3, 5, 7, 9 L = LOW Voltage Level Z = High Impedance 2001 Fairchild Semiconductor Corporation DS011611 74LVQ240 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current ICC or IGND Storage Temperature TSTG DC Latch-Up Source or Sink Current −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±400 mA −65°C to +150°C ±300 mA Recommended Operating Conditions Note 2 Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate VIN 0.8V to 2.0V VCC 3.0V 2.0V to 3.6V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Note 2 Unused inputs must be held HIGH or LOW. They may not float. DC Electrical Characteristics

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74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs
74LVQ240 Low Voltage Octal Buffer/Line Driver with 3-STATE Outputs

The LVQ240 is an inverting octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved PC board density.
s Ideal for low power/low noise 3.3V applications s Implements patented EMI reduction circuitry s Available in SOIC JEDEC, SOIC EIAJ, and QSOP pack-
ages s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Improved latch-up immunity s Guaranteed incident wave switching into s 4 kV minimum ESD immunity
Ordering Code:

Order Number Package Number

Package Description
74LVQ240SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74LVQ240SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74LVQ240QSC

MQA20
20-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

IEEE/IEC

Pin Names

OE1, OE2

Description 3-STATE Output Enable Inputs Outputs

Truth Tables

Connection Diagram

Inputs

Outputs

Pins 12, 14, 16, 18 H L Z

Inputs

OE2 L H

H = HIGH Voltage Level X = Immaterial

Outputs

Pins 3, 5, 7, 9

L = LOW Voltage Level Z = High Impedance
2001 Fairchild Semiconductor Corporation DS011611
74LVQ240

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current

ICC or IGND Storage Temperature TSTG DC Latch-Up Source or

Sink Current
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
±50 mA
±400 mA −65°C to +150°C
±300 mA

Recommended Operating Conditions Note 2

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate

VIN 0.8V to 2.0V VCC 3.0V
2.0V to 3.6V 0V to VCC 0V to VCC
−40°C to +85°C
125 mV/ns

Note 1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation.

Note 2 Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

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Datasheet ID: 74LVQ240QSC 513409