74LVQ174SCX

74LVQ174SCX Datasheet

74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset

Part	Datasheet
74LVQ174SCX	74LVQ174SCX (pdf)

Related Parts	Information
74LVQ174SJ	74LVQ174SJ
74LVQ174SJX	74LVQ174SJX
74LVQ174SC	74LVQ174SC

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74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset 74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset The LVQ174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flipflops. s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Guaranteed incident wave switching into Ordering Code: Order Number Package Number Package Description 74LVQ174SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74LVQ174SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names CP MR Description Data Inputs Clock Pulse Input Master Reset Input Outputs 2001 Fairchild Semiconductor Corporation DS011353 74LVQ174 Functional Description Truth Table The LVQ174 consists of six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The Clock CP and Inputs Master Reset MR are common to all flip-flops. Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW-to-HIGH Clock CP transition. A LOW input to the Master Reset MR will force all outputs LOW independent of Clock or Data inputs. The LVQ174 is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements. H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Transition Logic Diagram Output Q L H L Q Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74LVQ174 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current ICC or IGND Storage Temperature TSTG DC Latch-Up Source or Sink Current −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±200 mA −65°C to +150°C ±100 mA Recommended Operating Conditions Note 2

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74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset
74LVQ174 Low Voltage Hex D-Type Flip-Flop with Master Reset

The LVQ174 is a high-speed hex D-type flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition. The device has a Master Reset to simultaneously clear all flipflops.
s Ideal for low power/low noise 3.3V applications s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Guaranteed incident wave switching into
Ordering Code:

Order Number Package Number

Package Description
74LVQ174SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74LVQ174SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names CP MR

Description Data Inputs Clock Pulse Input Master Reset Input

Outputs
2001 Fairchild Semiconductor Corporation DS011353
74LVQ174

Functional Description

Truth Table

The LVQ174 consists of six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The Clock CP and

Inputs

Master Reset MR are common to all flip-flops. Each D
input’s state is transferred to the corresponding flip-flop’s
output following the LOW-to-HIGH Clock CP transition. A

LOW input to the Master Reset MR will force all outputs

LOW independent of Clock or Data inputs. The LVQ174 is
useful for applications where the true output only is
required and the Clock and Master Reset are common to all storage elements.

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Transition

Logic Diagram

Output

Q L H L Q

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74LVQ174

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current

ICC or IGND Storage Temperature TSTG DC Latch-Up Source or

Sink Current
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
±50 mA
±200 mA −65°C to +150°C
±100 mA

Recommended Operating Conditions Note 2

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Datasheet ID: 74LVQ174SCX 513408