74LCXZ245WMX

74LCXZ245WMX Datasheet

74LCXZ245 Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs

Part	Datasheet
74LCXZ245WMX	74LCXZ245WMX (pdf)

Related Parts	Information
74LCXZ245MTC	74LCXZ245MTC
74LCXZ245MTCX	74LCXZ245MTCX
74LCXZ245SJX	74LCXZ245SJX
74LCXZ245SJ	74LCXZ245SJ
74LCXZ245WM	74LCXZ245WM
74LCXZ245MSA	74LCXZ245MSA
74LCXZ245MSAX	74LCXZ245MSAX

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74LCXZ245 Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs 74LCXZ245 Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs The 74LCXZ245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage 2.5V and 3.3V VCC applications with capability of interfacing to a 5V signal environment. The T/R input determines the direction of data flow through the device. The OE input disables both the A and B ports by placing them in a high impedance state. The 74LCXZ245 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. When VCC is between 0V and 1.5V, the 74LCXZ245 is on the high impedance state during power up or power down. This places the outputs in the high impedance Z state preventing intermittent low impedance loading or glitching in bus oriented applications. s 5V tolerant inputs and outputs s VCC specifications provided s ns tPD max VCC 3.3V , 10 PA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s r24 mA output drive VCC 3.0V s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model ! 2000V Machine model ! 200V Note 1 To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74LCXZ245WM M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74LCXZ245SJ M20D Pb-Free 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74LCXZ245MSA MSA20 20-Lead Shrink Small Outline Package SSOP , JEDEC MO-150, 5.3mm Wide 74LCXZ245MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Logic Symbol Connection Diagram Pin Descriptions Pin Names OE T/R Output Enable Input Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs 2005 Fairchild Semiconductor Corporation DS500362 74LCXZ245 Truth Table Inputs Outputs Bus B0 B7 Data to Bus A0 A7 Bus A0 A7 Data to Bus B0 B7 X HIGH Z State on A0 A7, B0 B7 Note 2 H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Note 2 Unused bus terminals during HIGH Z State must be held HIGH or LOW. Logic Diagram 74LCXZ245 Absolute Maximum Ratings Note 3 Parameter Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current IO ICC IGND TSTG DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value to VCC r50 r100 to Conditions Output in 3-STATE Output in HIGH or LOW State Note 4 VI GND VO GND VO ! VCC Units V mA qC Recommended Operating Conditions Note 5 Parameter Units Supply Voltage Input Voltage Output Voltage Operating

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74LCXZ245 Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs
74LCXZ245 Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs

The 74LCXZ245 contains eight non-inverting bidirectional buffers with 3-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage 2.5V and 3.3V VCC applications with capability of interfacing to a 5V signal environment. The T/R input determines the direction of data flow through the device. The OE input disables both the A and B ports by placing them in a high impedance state.

The 74LCXZ245 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. When VCC is between 0V and 1.5V, the 74LCXZ245 is on the high impedance state during power up or power down. This places the outputs in the high impedance Z state preventing intermittent low impedance loading or glitching in bus oriented applications.
s 5V tolerant inputs and outputs s VCC specifications provided s ns tPD max VCC 3.3V , 10 PA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s r24 mA output drive VCC 3.0V s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance:

Human body model ! 2000V Machine model ! 200V

Note 1 To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Description
74LCXZ245WM

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74LCXZ245SJ

M20D

Pb-Free 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74LCXZ245MSA

MSA20
20-Lead Shrink Small Outline Package SSOP , JEDEC MO-150, 5.3mm Wide
74LCXZ245MTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B.

Logic Symbol

Connection Diagram

Pin Descriptions

Pin Names

OE T/R

Output Enable Input Transmit/Receive Input Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs
2005 Fairchild Semiconductor Corporation DS500362
74LCXZ245

Truth Table

Inputs

Outputs

Bus B0 B7 Data to Bus A0 A7

Bus A0 A7 Data to Bus B0 B7

X HIGH Z State on A0 A7, B0 B7 Note 2

H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance

Note 2 Unused bus terminals during HIGH Z State must be held HIGH or LOW.

Logic Diagram
74LCXZ245

Absolute Maximum Ratings Note 3

Parameter

Supply Voltage

DC Input Voltage

DC Output Voltage

DC Input Diode Current

DC Output Diode Current

IO ICC IGND TSTG

DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature

Value to VCC
r50 r100 to

Conditions

Output in 3-STATE Output in HIGH or LOW State Note 4 VI GND VO GND VO ! VCC

Units V
mA qC

Recommended Operating Conditions Note 5

Parameter

Units

Supply Voltage

Input Voltage

Output Voltage

Operating

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Datasheet ID: 74LCXZ245WMX 513396