74LCX646MTC

74LCX646MTC Datasheet

74LCX646 Low Voltage Octal Transceiver/Register with 5V Tolerant Inputs and Outputs

Part	Datasheet
74LCX646MTC	74LCX646MTC (pdf)

Related Parts	Information
74LCX646WM	74LCX646WM
74LCX646WMX	74LCX646WMX
74LCX646MTCX	74LCX646MTCX
74LCX646MSA	74LCX646MSA
74LCX646MSAX	74LCX646MSAX

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74LCX646 Low Voltage Octal Transceiver/Register with 5V Tolerant Inputs and Outputs 74LCX646 Low Voltage Octal Transceiver/Register with 5V Tolerant Inputs and Outputs The LCX646 consists of registered bus transceiver circuits, D-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate pin CPAB or CPBA see Functional Description . The LCX646 is designed for low voltage 2.5V or 3.3V VCC applications with capability of interfacing to a 5V signal environment. The LCX646 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. s 5V tolerant inputs and outputs s 2.3V − 3.6V VCC specifications provided s ns tPD max VCC = 3.3V , 10 µA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s ±24 mA output drive VCC = 3.0V s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 200V Note 1 To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74LCX646WM M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74LCX646MSA MSA24 24-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide 74LCX646MTC MTC24 24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names CPAB, CPBA SAB, SBA OE DIR Description Data Register A Inputs Data Register A Outputs Data Register B Inputs Data Register B Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Input Direction Control Input 2001 Fairchild Semiconductor Corporation DS011997 74LCX646 Logic Symbols IEEE/IEC Truth Table Note 2 OE Inputs Data I/O DIR CPAB CPBA SAB SBA Function X H or L H or L X Isolation X Input Clock An Data into A Register Clock Bn Data into B Register An to Time Transparent Mode X Input Output Clock An Data into A Register H or L X A Register to Bn Stored Mode Clock An Data into A Register and Output to Bn Bn to Time Transparent Mode L Output Input Clock Bn Data into B Register X H or L X B Register to An Stored Mode Clock Bn Data into B Register and Output to An H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Transition Note 2 The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. 74LCX646 Functional Description In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select SAB, SBA controls can multiplex stored and real-time. The examples shown below demonstrate the four fundamental bus-management functions that can be performed. The direction control DIR determines which bus will receive data when OE is LOW. In the isolation mode OE HIGH , A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two busses, A or B, may be driven at a time. Real-Time Transfer Bus B to Bus A Real-Time Transfer Bus A to Bus B OE DIR CPAB CPBA SAB SBA Transfer Storage Data to A or B OE DIR CPAB CPBA SAB SBA Storage

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74LCX646 Low Voltage Octal Transceiver/Register with 5V Tolerant Inputs and Outputs
74LCX646 Low Voltage Octal Transceiver/Register with 5V Tolerant Inputs and Outputs

The LCX646 consists of registered bus transceiver circuits, D-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate pin CPAB or CPBA see Functional Description .

The LCX646 is designed for low voltage 2.5V or 3.3V VCC applications with capability of interfacing to a 5V signal environment.

The LCX646 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation.
s 5V tolerant inputs and outputs s 2.3V − 3.6V VCC specifications provided s ns tPD max VCC = 3.3V , 10 µA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s ±24 mA output drive VCC = 3.0V s Implements patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance:

Human body model > 2000V Machine model > 200V

Note 1 To ensure the high-impedance state during power up or down, OE should be tied to VCC through a pull-up resistor the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Description
74LCX646WM

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74LCX646MSA

MSA24
24-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide
74LCX646MTC

MTC24
24-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

CPAB, CPBA SAB, SBA OE DIR

Description Data Register A Inputs Data Register A Outputs Data Register B Inputs Data Register B Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Input Direction Control Input
2001 Fairchild Semiconductor Corporation DS011997
74LCX646

Logic Symbols

IEEE/IEC

Truth Table

Note 2 OE

Inputs

Data I/O

DIR CPAB CPBA SAB SBA

Function

X H or L H or L X

Isolation

X Input Clock An Data into A Register

Clock Bn Data into B Register

An to Time Transparent Mode

X Input Output Clock An Data into A Register

H or L X

A Register to Bn Stored Mode Clock An Data into A Register and Output to Bn

Bn to Time Transparent Mode

L Output Input Clock Bn Data into B Register

X H or L X

B Register to An Stored Mode Clock Bn Data into B Register and Output to An

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Transition

Note 2 The data output functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
74LCX646

Functional Description

In the transceiver mode, data present at the HIGH impedance port may be stored in either the A or B register or both. The select SAB, SBA controls can multiplex stored and real-time. The examples shown below demonstrate the four fundamental bus-management functions that can be performed.

The direction control DIR determines which bus will receive data when OE is LOW. In the isolation mode OE HIGH , A data may be stored in one register and/or B data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two busses, A or B, may be driven at a time.

Real-Time Transfer Bus B to Bus A

Real-Time Transfer Bus A to Bus B

OE DIR CPAB CPBA SAB SBA

Transfer Storage Data to A or B

OE DIR CPAB CPBA SAB SBA

Storage

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Datasheet ID: 74LCX646MTC 513390