74LCX32500GX

74LCX32500GX Datasheet

74LCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs

Part	Datasheet
74LCX32500GX	74LCX32500GX (pdf)

Related Parts	Information
74LCX32500G	74LCX32500G

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74LCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs 74LCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs These 36-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable LEAB and LEBA , and clock CLKAB and CLKBA inputs. The LCX32500 is designed for low voltage 2.5V or 3.3V VCC applications with the capability of interfacing to a 5V signal environment. The LCX32500 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power. s 5V tolerant inputs and outputs s VCC specifications provided s ns tPD max VCC = 3.3V , 20 µA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s ±24 mA output drive VCC = 3.0V s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance: Human body model > 2000V Machine model > 200V s Packaged in plastic Fine-Pitch Ball Grid Array FBGA Note 1 To ensure the high-impedance state during power up or down, OE should be tied to VCC and OE tied to GND through a resistor the minimum value or the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74LCX32500G Note 2 Note 3 BGA114A 114-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide Note 2 Ordering code “G” indicates Trays. Note 3 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2002 Fairchild Semiconductor Corporation DS500406 74LCX32500 Connection Diagram Top Thru View Truth Table Note 4 Inputs Output OEABn LEABn CLKABn An H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance B0 Note 5 B0 Note 6 Note 4 A-to-B data flow is shown B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 5 Output level before the indicated steady-state input conditions were established. Note 6 Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW. Pin Descriptions Pin Names 1A1 - 1A18 2A1 - 2A18 1B1 - 1B18 2B1 - 2B18 Data Register A Inputs/3-STATE Outputs Data Register B Inputs/3-STATE Outputs CLKAB1, CLKBA1 Clock Pulse Inputs CLKAB2, CLKBA2 LEAB1, LEBA1 Latch Enable Inputs LEAB2, LEBA2 OEAB1, OEBA1 OEAB2, OEBA2 Output Enable Inputs FBGA Pin Assignments 1A2 1A1 LEAB1 CLKAB1 1B1 1A4 1A3 OEAB1 GND 1A6 1A5 GND 1A8 1A7 VCC E 1A10 1A9 GND 1B9 1B10 1A12 1A11 GND 1B11 1B12 G 1A14 1A13 VCC 1B13 1B14 1A15 1A16 GND 1B16 1B15 1A17 1A18 OEBA1 CLKBA1 1B18 1B17 NC LEAB2 LEBA1 GND CLKAB2 NC 2A2 2A1 OEAB2 GND 2A4 2A3 GND 2A6 2A5 VCC 2A8 2A7 GND R 2A10 2A9 GND

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74LCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs
74LCX32500 Low Voltage 36-Bit Universal Bus Transceivers with 5V Tolerant Inputs and Outputs

These 36-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable LEAB and LEBA , and clock CLKAB and CLKBA inputs.

The LCX32500 is designed for low voltage 2.5V or 3.3V VCC applications with the capability of interfacing to a 5V signal environment.

The LCX32500 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining CMOS low power.
s 5V tolerant inputs and outputs s VCC specifications provided s ns tPD max VCC = 3.3V , 20 µA ICC max s Power down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s ±24 mA output drive VCC = 3.0V s Uses patented noise/EMI reduction circuitry s Latch-up performance exceeds 500 mA s ESD performance:

Human body model > 2000V Machine model > 200V s Packaged in plastic Fine-Pitch Ball Grid Array FBGA

Note 1 To ensure the high-impedance state during power up or down, OE should be tied to VCC and OE tied to GND through a resistor the minimum value or the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Description
74LCX32500G Note 2 Note 3

BGA114A 114-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide
Note 2 Ordering code “G” indicates Trays.
Note 3 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2002 Fairchild Semiconductor Corporation DS500406
74LCX32500

Connection Diagram

Top Thru View

Truth Table Note 4

Inputs

Output

OEABn LEABn CLKABn An

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance

B0 Note 5 B0 Note 6

Note 4 A-to-B data flow is shown B-to-A flow is similar but uses OEBA, LEBA, and CLKBA.

Note 5 Output level before the indicated steady-state input conditions were established.

Note 6 Output level before the indicated steady-state input conditions were established, provided that CLKAB was LOW before LEAB went LOW.

Pin Descriptions

Pin Names
1A1 - 1A18 2A1 - 2A18 1B1 - 1B18 2B1 - 2B18

Data Register A Inputs/3-STATE Outputs Data Register B Inputs/3-STATE Outputs

CLKAB1, CLKBA1 Clock Pulse Inputs CLKAB2, CLKBA2 LEAB1, LEBA1 Latch Enable Inputs LEAB2, LEBA2

OEAB1, OEBA1 OEAB2, OEBA2

Output Enable Inputs

FBGA Pin Assignments
1A2 1A1 LEAB1 CLKAB1 1B1
1A4 1A3 OEAB1 GND
1A6 1A5 GND
1A8 1A7 VCC

E 1A10 1A9 GND
1B9 1B10
1A12 1A11 GND
1B11 1B12

G 1A14 1A13 VCC
1B13 1B14
1A15 1A16 GND
1B16 1B15
1A17 1A18 OEBA1 CLKBA1 1B18 1B17

NC LEAB2 LEBA1 GND CLKAB2 NC
2A2 2A1 OEAB2 GND
2A4 2A3 GND
2A6 2A5 VCC
2A8 2A7 GND

R 2A10 2A9 GND

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Datasheet ID: 74LCX32500GX 513389