74LCX08MTCX_SF501639
74LCX08MTCX_SF501639 Datasheet
74LCX08 Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs
| Part | Datasheet |
|---|---|
74LCX08MTCX_SF501639 |
74LCX08MTCX_SF501639 (pdf) |
| Related Parts | Information |
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74LCX08SJ |
74LCX08SJ |
| PDF Datasheet Preview |
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| 74LCX08 Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs February 2008 74LCX08 Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs • 5V tolerant inputs • VCC specifications provided • 5.5ns tPD max. VCC = 3.3V , 10µA ICC max. • Power down high impedance inputs and outputs • ±24mA output drive VCC = 3.0V • Implements patented noise/EMI reduction circuitry • Latch-up performance exceeds JEDEC 78 conditions • ESD performance: Human body model > 2000V Machine model > 150V • Leadless DQFN package The LCX08 contains four 2-input AND gates. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems. The 74LVX08 is fabricated with advanced CMOS technology to achieve high speed operation while maintaining CMOS low power dissipation. Ordering Information Package Order Number Package Description 74LCX08M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74LCX08SJ 74LCX08BQX 1 M14D MLP14A 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 14-Terminal Depopulated Quad Very-Thin Flat Pack No Leads DQFN , JEDEC MO-241, x 3.0mm 74LCX08MTC MTC14 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Note DQFN package available in Tape and Reel only. Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC J-STD-020B standard. 74LCX08 Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs Connection Diagrams Pin Assignments for SOIC, SOP, and TSSOP Logic Symbol IEEE/IEC Pad Assignments for DQFN Top View Pin Description Pin Names An, Bn On Description Inputs Outputs 1995 Fairchild Semiconductor Corporation 74LCX08 Low Voltage Quad 2-Input AND Gate with 5V Tolerant Inputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VCC VI VO IIK IOK IO ICC IGND TSTG Supply Voltage DC Input Voltage DC Output Voltage, Output in HIGH or LOW State 2 DC Input Diode Current, VI < GND DC Output Diode Current VO < GND VO > VCC DC Output Source/Sink Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Note IO Absolute Maximum Rating must be observed. Rating to +7.0V to +7.0V to VCC + 0.5V +50mA ±50mA ±100mA ±100mA to +150°C Recommended Operating Conditions 3 The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Parameter Supply Voltage Operating Data Retention VI VO IOH / IOL Input Voltage Output Voltage, HIGH or LOW State Output Current VCC = VCC = VCC = Free-Air Operating Temperature Input Edge Rate, VIN = VCC = 3.0V Note Unused inputs must be held HIGH or LOW. They may not float. Min. 0 Max. ±24 ±12 ±8 85 10 Units V mA °C ns / V 1995 Fairchild Semiconductor Corporation |
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