74F827SPC

74F827SPC Datasheet

74F827<br>• 74F828 10-Bit Buffers/Line Drivers

Part	Datasheet
74F827SPC	74F827SPC (pdf)

Related Parts	Information
74F827SC	74F827SC
74F828SPC	74F828SPC
74F827SCX	74F827SCX

PDF Datasheet Preview
74F827 • 74F828 10-Bit Buffers/Line Drivers 74F827 • 74F828 10-Bit Buffers/Line Drivers The 74F827 and 74F828 10-bit bus buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NOR output enables for maximum control flexibility. The 74F828 is an inverting version of the 74F827. s 3-STATE output s 74F828 is inverting Ordering Code: Order Number Package Number Package Description 74F827SC Note 1 M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F827SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74F828SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F828SPC Note 1 N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Note 1 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams 74F827 74F828 2004 Fairchild Semiconductor Corporation DS009598 74F827 • 74F828 Logic Symbols 74F827 IEEE/IEC 74F827 74F828 IEEE/IEC 74F828 Unit Loading/Fan Out Pin Names OE1, OE2 Output Enable Input Data Inputs Data Outputs, 3-STATE Functional Description The 74F827 and 74F828 are line drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density. The devices have 3-STATE outputs controlled by the Output Enable OE pins. The outputs can sink 64 mA and source 15 mA. Input clamp diodes limit high-speed termination effects. U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA −12 mA/64 mA 48 mA Function Table Inputs Outputs 74F827 74F828 H = HIGH Voltage level L = LOW Voltage Level Z = High Impedance X = Immaterial Function Transparent High Z 74F827 • 74F828 Logic Diagrams 74F827 74F828 Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F827 • 74F828 Absolute Maximum Ratings Note 2 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 3

PDF Datasheet Preview

74F827
• 74F828 10-Bit Buffers/Line Drivers
74F827
• 74F828 10-Bit Buffers/Line Drivers

The 74F827 and 74F828 10-bit bus buffers provide high performance bus interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NOR output enables for maximum control flexibility.

The 74F828 is an inverting version of the 74F827.
s 3-STATE output s 74F828 is inverting
Ordering Code:

Order Number Package Number

Package Description
74F827SC Note 1

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F827SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74F828SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F828SPC Note 1

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Note 1 Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams
74F827
74F828
2004 Fairchild Semiconductor Corporation DS009598
74F827
• 74F828

Logic Symbols
74F827

IEEE/IEC 74F827
74F828

IEEE/IEC 74F828

Unit Loading/Fan Out

Pin Names

OE1, OE2

Output Enable Input Data Inputs Data Outputs, 3-STATE

Functional Description

The 74F827 and 74F828 are line drivers designed to be employed as memory address drivers, clock drivers and bus-oriented transmitters/receivers which provide improved PC board density. The devices have 3-STATE outputs controlled by the Output Enable OE pins. The outputs can sink 64 mA and source 15 mA. Input clamp diodes limit high-speed termination effects.

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL
20 µA/−0.6 mA 20 µA/−0.6 mA −12 mA/64 mA 48 mA

Function Table

Inputs

Outputs
74F827 74F828

H = HIGH Voltage level L = LOW Voltage Level Z = High Impedance X = Immaterial

Function

Transparent High Z
74F827
• 74F828

Logic Diagrams
74F827
74F828

Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F827
• 74F828

Absolute Maximum Ratings Note 2

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 3

More datasheets: DM74S32N | QR08B-4/203229 | QR08A-2/205803 | QR08A-4/207785 | QR08B-2/203233 | 855-11657 | 855-11656 | 3BWD5V | 74F827SC | 74F828SPC

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Datasheet ID: 74F827SPC 513376