74F825SCX

74F825SCX Datasheet

74F825 8-Bit D-Type Flip-Flop

Part	Datasheet
74F825SCX	74F825SCX (pdf)

Related Parts	Information
74F825SC	74F825SC
74F825SPC	74F825SPC

PDF Datasheet Preview
74F825 8-Bit D-Type Flip-Flop 74F825 8-Bit D-Type Flip-Flop The 74F825 is an 8-bit buffered register. It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included in the 74F825 are multiple enables that allow multi-user control of the interface. s 3-STATE output s Clock enable and clear s Multiple output enables Ordering Code: Order Number Package Number Package Description 74F825SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F825SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009597 74F825 Unit Loading/Fan Out Pin Names OE1, OE2, OE3 EN CLR CP Data Inputs 3-STATE Data Outputs Output Enable Input Clock Enable Clear Clock Input U.L. HIGH/LOW 150/40 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA −3 mA/24 mA 20 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.2 mA Functional Description The 74F825 consists of eight D-type edge-triggered flip-flops. This device has 3-STATE true outputs and is organized in broadside pinning. In addition to the clock and output enable pins, the buffered clock CP and buffered Output Enable OE are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition. With the OE LOW the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The 74F825 has Clear CLR and Clock Enable EN pins. When the CLR is LOW and the OE is LOW the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH the outputs do not change state, regardless of the data or clock input transitions. Logic Diagram Function Table Inputs Internal Output OE CLR EN CP D Q Function H L H X NC Z Hold H L X NC Z Hold H X NC Z Hold L H X NC NC Hold H L X XX H Z Clear H L H L L Clear Z Load Z Load L Data Available H Data Available L H L H X NC NC No Change in Data L H L X NC NC No Change in Data L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial = High Impedance = LOW-to-HIGH Transition NC = No Change Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F825

PDF Datasheet Preview

74F825 8-Bit D-Type Flip-Flop
74F825 8-Bit D-Type Flip-Flop

The 74F825 is an 8-bit buffered register. It has Clock Enable and Clear features which are ideal for parity bus interfacing in high performance microprogramming systems. Also included in the 74F825 are multiple enables that allow multi-user control of the interface.
s 3-STATE output s Clock enable and clear s Multiple output enables
Ordering Code:

Order Number Package Number

Package Description
74F825SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F825SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009597
74F825

Unit Loading/Fan Out

Pin Names

OE1, OE2, OE3 EN CLR CP

Data Inputs 3-STATE Data Outputs Output Enable Input Clock Enable Clear Clock Input

U.L. HIGH/LOW
150/40

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA −3 mA/24 mA 20 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.2 mA

Functional Description

The 74F825 consists of eight D-type edge-triggered flip-flops. This device has 3-STATE true outputs and is organized in broadside pinning. In addition to the clock and output enable pins, the buffered clock CP and buffered Output Enable OE are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition. With the OE LOW the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The 74F825 has Clear CLR and Clock Enable EN pins. When the CLR is LOW and the OE is LOW the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH the outputs do not change state, regardless of the data or clock input transitions.

Logic Diagram

Function Table

Inputs

Internal Output

OE CLR EN CP D Q

Function

H L H X NC

Z Hold

H L X NC

Z Hold

H X NC

Z Hold

L H X NC

NC Hold

H L X XX H

Z Clear

H L H L

L Clear Z Load Z Load L Data Available H Data Available

L H L H X NC

NC No Change in Data

L H L X NC

NC No Change in Data

L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial
= High Impedance = LOW-to-HIGH Transition NC = No Change

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F825

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Datasheet ID: 74F825SCX 513375