74F823SC

74F823SC Datasheet

74F823 9-Bit D-Type Flip-Flop

Part	Datasheet
74F823SC	74F823SC (pdf)

Related Parts	Information
74F823SCX	74F823SCX
74F823SPC	74F823SPC

PDF Datasheet Preview
74F823 9-Bit D-Type Flip-Flop 74F823 9-Bit D-Type Flip-Flop The 74F823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. s 3-STATE outputs s Clock Enable and Clear Ordering Code: Order Number Package Number Package Description 74F823SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F823SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009596 74F823 Unit Loading/Fan Out Pin Names OE CLR CP EN Data Inputs Output Enable Input Clear Clock Input Clock Enable 3-STATE Outputs Functional Description The 74F823 device consists of nine D-type edge-triggered flip-flops. It has 3-STATE true outputs and is organized in broadside pinning. The buffered Clock CP and buffered Output Enable OE are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition. With the OE LOW the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. In addition to the Clock and Output Enable pins, the 74F823 has Clear CLR and Clock Enable EN pins. When the CLR is LOW and the OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH, the outputs do not change state regardless of the data or clock inputs transitions. This device is ideal for parity bus interfacing in high performance systems. Logic Diagram U.L. HIGH/LOW 150/40 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.2 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA Function Table Inputs Internal Output OE CLR EN CP D Q Function H L H X NC Z Hold H L X NC Z Hold H X NC Z Hold L H X NC NC Hold H L X XX H Z Clear H L H L L Clear Z Load Z Load L Data Available H Data Available L H L H X NC NC No Change in Data L H L X NC NC No Change in Data L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial = High Impedance = LOW-to-HIGH Transition NC = No Change Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

PDF Datasheet Preview

74F823 9-Bit D-Type Flip-Flop
74F823 9-Bit D-Type Flip-Flop

The 74F823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems.
s 3-STATE outputs s Clock Enable and Clear
Ordering Code:

Order Number Package Number

Package Description
74F823SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F823SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009596
74F823

Unit Loading/Fan Out

Pin Names

OE CLR CP EN

Data Inputs Output Enable Input Clear Clock Input Clock Enable 3-STATE Outputs

Functional Description

The 74F823 device consists of nine D-type edge-triggered flip-flops. It has 3-STATE true outputs and is organized in broadside pinning. The buffered Clock CP and buffered Output Enable OE are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold times requirements on the LOW-to-HIGH CP transition. With the OE LOW the contents of the flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. In addition to the Clock and Output Enable pins, the 74F823 has Clear CLR and Clock Enable EN pins.

When the CLR is LOW and the OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH, the outputs do not change state regardless of the data or clock inputs transitions. This device is ideal for parity bus interfacing in high performance systems.

Logic Diagram

U.L. HIGH/LOW
150/40

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.2 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA

Function Table

Inputs

Internal Output

OE CLR EN CP D Q

Function

H L H X NC

Z Hold

H L X NC

Z Hold

H X NC

Z Hold

L H X NC

NC Hold

H L X XX H

Z Clear

H L H L

L Clear Z Load Z Load L Data Available H Data Available

L H L H X NC

NC No Change in Data

L H L X NC

NC No Change in Data

L = LOW Voltage Level H = HIGH Voltage Level X = Immaterial
= High Impedance = LOW-to-HIGH Transition NC = No Change

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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Datasheet ID: 74F823SC 513374