74F74SJX

74F74SJX Datasheet

74F74 Dual D-Type Positive Edge-Triggered Flip-Flop

Part	Datasheet
74F74SJX	74F74SJX (pdf)

Related Parts	Information
74F74SCX	74F74SCX
74F74SJ	74F74SJ
74F74PC	74F74PC
74F74SC	74F74SC

PDF Datasheet Preview
74F74 Dual D-Type Positive Edge-Triggered Flip-Flop 74F74 Dual D-Type Positive Edge-Triggered Flip-Flop The F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Ordering Code: Order Number Package Number Package Description 74F74SC M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow 74F74SJ M14D 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F74PC N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009469 74F74 Unit Loading/Fan Out Pin Names D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2 Truth Table Data Inputs Clock Pulse Inputs Active Rising Edge Direct Clear Inputs Active LOW Direct Set Inputs Active LOW Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.8 mA 20 µA/−1.8 mA −1 mA/20 mA Inputs Outputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Q0 = Previous Q before LOW-to-HIGH Clock Transition Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F74 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V Current Applied to Output in LOW State Max twice the rated IOL mA ESD Last Passing Voltage Min 4000V Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

PDF Datasheet Preview

74F74 Dual D-Type Positive Edge-Triggered Flip-Flop
74F74 Dual D-Type Positive Edge-Triggered Flip-Flop

The F74 is a dual D-type flip-flop with Direct Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to
the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs:

LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD
makes both Q and Q HIGH
Ordering Code:

Order Number Package Number

Package Description
74F74SC

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow
74F74SJ

M14D
14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F74PC

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009469
74F74

Unit Loading/Fan Out

Pin Names

D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2

Truth Table

Data Inputs Clock Pulse Inputs Active Rising Edge Direct Clear Inputs Active LOW Direct Set Inputs Active LOW Outputs

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.8 mA 20 µA/−1.8 mA −1 mA/20 mA

Inputs

Outputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Q0 = Previous Q before LOW-to-HIGH Clock Transition Lower case letters indicate the state of the referenced input or output one setup time prior to the LOW-to-HIGH clock transition.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F74

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output
in LOW State Max
twice the rated IOL mA

ESD Last Passing Voltage Min
4000V

Recommended Operating Conditions

Free Air Ambient Temperature Supply Voltage
0°C to +70°C +4.5V to +5.5V

Note 1 Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied.

More datasheets: 480-001 | ELD-511USOWA/S530-A4 | MV5094A | 12014 | DFR0095 | DFR0334 | 3517 | B39401R983U410 | 74F74SCX | 74F74SJ

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 74F74SJX Datasheet file may be downloaded here without warranties.

Datasheet ID: 74F74SJX 513369