74F673ASC

74F673ASC Datasheet

74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register

Part	Datasheet
74F673ASC	74F673ASC (pdf)

Related Parts	Information
74F673APC	74F673APC
74F673ASPC	74F673ASPC

PDF Datasheet Preview
74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register 74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register The 74F673A contains a 16-bit serial-in, serial-out shift register and a 16-bit Parallel-Out storage register. A single pin serves either as an input for serial entry or as a 3-STATE serial output. In the Serial-Out mode, the data recirculates in the shift register. By means of a separate clock, the contents of the shift register are transferred to the storage register for parallel outputting. The contents of the storage register can also be parallel loaded back into the shift register. A HIGH signal on the Chip Select input prevents both shifting and parallel transfer. The storage register may be cleared via STMR. s Serial-to-parallel converter s 16-bit serial I/O shift register s 16-bit parallel-out storage register s Recirculating serial shifting s Recirculating parallel transfer s Common serial data I/O pin s Slim 24 lead package Ordering Code: Order Number Package Number Package Description 74F673ASC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F673APC N24A 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-011, Wide 74F673ASPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols IEEE/IEC Connection Diagram 2000 Fairchild Semiconductor Corporation DS009585 74F673A Unit Loading/Fan Out Pin Names CS SHCP STMR STCP R/W SI/O Chip Select Input Active LOW Shift Clock Pulse Input Active Falling Edge Store Master Reset Input Active LOW Store Clock Pulse Input Read/Write Input Serial Data Input or 3-STATE Serial Output Parallel Data Outputs U.L. HIGH/LOW 150/40 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 70 µA/−0.6 mA −3 mA/24 mA −1 mA/20 mA Functional Description The 16-bit shift register operates in one of four modes, as indicated in the Shift Register Operations Table. A HIGH signal on the Chip Select CS input prevents clocking and forces the Serial Input/Output SI/O 3-STATE buffer into the high impedance state. During serial shift-out operations, the SI/O buffer is active i.e., enabled and the output data is also recirculated back into the shift register. When parallel loading the shift register from the storage register, serial shifting is inhibited. The storage register has an asynchronous master reset STMR input that overrides all other inputs and forces the outputs LOW. The storage register is in the Hold mode when either CS or the Read/Write R/W input is HIGH. With CS and R/W both LOW, the storage register is parallel loaded from the shift register. Shift Register Operations Table Control Inputs SI/O CS R/W SHCP STCP Status Operating Mode X High Z Hold X Data In Serial Load L Data Out Serial Output H Active with Recirculation Parallel Load; H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = HIGH-to-LOW Transition No Shifting Storage Register Operations Table Control Inputs Operating STMR CS R/W STCP Mode X Reset Outputs LOW X Hold H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Transition X Hold Parallel Load

PDF Datasheet Preview

74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register
74F673A 16-Bit Serial-In, Serial/Parallel-Out Shift Register

The 74F673A contains a 16-bit serial-in, serial-out shift register and a 16-bit Parallel-Out storage register. A single pin serves either as an input for serial entry or as a 3-STATE serial output. In the Serial-Out mode, the data recirculates in the shift register. By means of a separate clock, the contents of the shift register are transferred to the storage register for parallel outputting. The contents of the storage register can also be parallel loaded back into the shift register. A HIGH signal on the Chip Select input prevents both shifting and parallel transfer. The storage register may be cleared via STMR.
s Serial-to-parallel converter s 16-bit serial I/O shift register s 16-bit parallel-out storage register s Recirculating serial shifting s Recirculating parallel transfer s Common serial data I/O pin s Slim 24 lead package
Ordering Code:

Order Number Package Number

Package Description
74F673ASC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F673APC

N24A
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-011, Wide
74F673ASPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

IEEE/IEC

Connection Diagram
2000 Fairchild Semiconductor Corporation DS009585
74F673A

Unit Loading/Fan Out

Pin Names

CS SHCP STMR STCP R/W SI/O

Chip Select Input Active LOW Shift Clock Pulse Input Active Falling Edge Store Master Reset Input Active LOW Store Clock Pulse Input Read/Write Input Serial Data Input or 3-STATE Serial Output Parallel Data Outputs

U.L. HIGH/LOW
150/40

Input IIH/IIL Output IOH/IOL
20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 70 µA/−0.6 mA −3 mA/24 mA −1 mA/20 mA

Functional Description

The 16-bit shift register operates in one of four modes, as indicated in the Shift Register Operations Table. A HIGH signal on the Chip Select CS input prevents clocking and forces the Serial Input/Output SI/O 3-STATE buffer into the high impedance state. During serial shift-out operations, the SI/O buffer is active i.e., enabled and the output data is also recirculated back into the shift register. When
parallel loading the shift register from the storage register, serial shifting is inhibited.

The storage register has an asynchronous master reset STMR input that overrides all other inputs and forces the outputs LOW. The storage register is in the Hold mode when either CS or the Read/Write R/W input is HIGH. With CS and R/W both LOW, the storage register is parallel loaded from the shift register.

Shift Register Operations Table

Control Inputs

SI/O

CS R/W SHCP STCP Status

Operating Mode

X High Z Hold

X Data In Serial Load L Data Out Serial Output

H Active
with Recirculation Parallel Load;

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = HIGH-to-LOW Transition

No Shifting

Storage Register Operations Table

Control Inputs

Operating

STMR CS R/W STCP

Mode

X Reset Outputs LOW

X Hold

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Transition

X Hold

Parallel Load

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Datasheet ID: 74F673ASC 513366