74F544SPC

74F544SPC Datasheet


74F544 Octal Registered Transceiver

Part Datasheet
74F544SPC 74F544SPC 74F544SPC (pdf)
Related Parts Information
74F544SC 74F544SC 74F544SC
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74F544 Octal Registered Transceiver
74F544 Octal Registered Transceiver

The 74F544 octal transceiver contains two sets of D-type latches for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent control of inputting and outputting in either direction of data flow. The A outputs are guaranteed to sink 24 mA while the B outputs are rated for 64 mA. The 74F544 inverts data in both directions.
s 8-bit octal transceiver s Back-to-back registers for storage s Separate controls for data flow in each direction s A outputs sink 24 mA, B outputs sink 64 mA
Ordering Code:

Order Number Package Number

Package Description
74F544SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F544MSA

MSA24
24-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide
74F544SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-100, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
1999 Fairchild Semiconductor Corporation DS009555
74F544

Unit Loading/Fan Out

Pin Names

OEAB OEBA CEAB CEBA LEAB LEBA

U.L. HIGH/LOW

A-to-B Output Enable Input Active LOW B-to-A Output Enable Input Active LOW A-to-B Enable Input Active LOW B-to-A Enable Input Active LOW A-to-B Latch Enable Input Active LOW B-to-A Latch Enable Input Active LOW A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B 3-STATE Outputs

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−1.2 mA 20 µA/−1.2 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 70 µA/−650 µA −3 mA/24 mA 20 mA 70 µA/−650 µA −12 mA/64 mA 48 mA

Functional Description

The 74F544 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable CEAB input must be LOW in order to enter data from or take data from as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable LEAB input makes the A-to-B latches transparent a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA inputs.

Logic Diagram

Data I/O Control Table

Inputs CEAB LEAB OEAB

Latch Status

Output Buffers

Latched

High Z

Latched

X Transparent

High Z

Driving

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

Note A-to-B data flow shown B-to-A flow control is the same, except using CEBA, LEBA and OEBA

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F544

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
More datasheets: PT8A3244WE | PT8A3240WEX | PT8A3244WEX | PT8A3244PEX | PT8A3245PEX | PT8A3246PEX | PT8A3247PEX | PT8A3243PEX | PT8A3245PE | 74F544SC


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Datasheet ID: 74F544SPC 513347