74F401PC

74F401PC Datasheet


74F401 CRC Generator/Checker

Part Datasheet
74F401PC 74F401PC 74F401PC (pdf)
PDF Datasheet Preview
74F401 CRC Generator/Checker
74F401 CRC Generator/Checker
s Eight selectable polynomials s Error indicator s Separate preset and clear controls s Automatic right justification s Fully compatible with all TTL logic families s 14-pin package s 9401 equivalent s Typical applications:

Floppy and other disk storage systems Digital cassette and cartridge systems Data communication systems
Ordering Code:

Order Number Package Number

Package Description
74F401SC

M14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow
74F401PC

N14A
14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram
1999 Fairchild Semiconductor Corporation DS009534
74F401

Unit Loading/Fan Out

Pin Names

D CP CWE P MR Q ER

Polynomial Select Inputs Data Input Clock Input Operates on HIGH-to-LOW Transition Check Word Enable Input Preset Active LOW Input Master Reset Active HIGH Input Data Output Error Output

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA

Functional Description

The 74F401 is a 16-bit programmable device which operates on serial data streams and provides a means of detecting transmission errors. Cyclic encoding and decoding schemes for error detection are based on polynomial manipulation in modulo arithmetic. For encoding, the data stream message polynomial is divided by a selected polynomial. This division results in a remainder which is appended to the message as check bits. For error checking, the bit stream containing both data and check bits is divided by the same selected polynomial. If there are no detectable errors, this division results in a zero remainder. Although it is possible to choose many generating polynomials of a given degree, standards exist that specify a small number of useful polynomials. The 74F401 implements the polynomials listed in Table 1 by applying the appropriate logic levels to the select pins S0, S1 and S2.

The 74F401 consists of a 16-bit register, a Read Only Memory ROM and associated control circuitry as shown in the block diagram. The polynomial control code presented at inputs S0, S1 and S2 is decoded by the ROM, selecting the desired polynomial by establishing shift mode operation on the register with Exclusive OR gates at appropriate inputs. To generate the check bits, the data stream is entered via the Data inputs D , using the HIGH-to-LOW
transition of the Clock input CP . This data is gated with the most significant output Q of the register, and controls the Exclusive OR gates Figure The Check Word Enable CWE must be held HIGH while the data is being entered. After the last data bit is entered, the CWE is brought LOW and the check bits are shifted out of the register and appended to the data bits using external gating Figure

To check an incoming message for errors, both the data and check bits are entered through the D input with the CWE input held HIGH. The 74F401 is not in the data path, but only monitors the message. The Error Output becomes valid after the last check bit has been entered into the 74F401 by a HIGH-to-LOW transition of CP. If no detectable errors have occurred during the data transmission, the resultant internal register bits are all LOW and the Error Output ER is LOW. If a detectable error has occurred, ER is HIGH.

A HIGH on the Master Reset input MR asynchronously clears the register. A LOW on the Preset input P asynchronously sets the entire register if the control code inputs specify a 16-bit polynomial in the case of 12- or 8-bit check polynomials only the most significant 12 or 8 register bits are set and the remaining bits are cleared.

Select Code

TABLE

Polynomial

X16 + X15 + X2 + 1 X16 + X14 + X + 1 X16 + X15 + X13 + X7 + X4 + X2 + X1 + 1 X12 + X11 + X3 + X2 + X + 1 X8 + X7 + X5 + X4 + X + 1 X8 + 1 X16 + X12 + X5 + 1 X16 + X11 + X4 + 1

CRC-12
74F401

Block Diagram

FIGURE Equivalent Circuit for X16 + X15 + X2 + 1

FIGURE Check Word Generation

Note 1 Check word Enable is HIGH while data is being clocked, LOW while transmission of check bits. Note 2 74F401 must be reset or preset before each computation. Note 3 CRC check bits are generated and appended to data bits.
74F401

Absolute Maximum Ratings Note 4

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 5
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 5
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
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Datasheet ID: 74F401PC 513334