74F378PC

74F378PC Datasheet

74F378 Parallel D-Type Register with Enable

Part	Datasheet
74F378PC	74F378PC (pdf)

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74F378 Parallel D-Type Register with Enable 74F378 Parallel D-Type Register with Enable The 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset. s 6-bit high-speed parallel register s Positive edge-triggered D-type inputs s Fully buffered common clock and enable inputs s Input clamp diodes limit high-speed termination effects s Full TTL and CMOS compatible Ordering Code: Order Number Package Number Package Description 74F378SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F378SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F378PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009526 74F378 Unit Loading/Fan Out Pin Names Enable Input Active LOW Data Inputs Clock Pulse Input Active Rising Edge Outputs U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA Functional Description The 74F378 consists of six edge-triggered D-type flip-flops with individual D inputs and Q inputs. The Clock CP and Enable E inputs are common to all flip-flops. When the E input is LOW, new data is entered into the register on the LOW-to-HIGH transition of the CP input. When the E input is HIGH the register will retain the present data independent of the CP input. Truth Table Inputs H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Clock Transition Output Qn No Change H L Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F378 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output −0.5V to VCC −0.5V to +5.5V Current Applied to Output in LOW State Max twice the rated IOL mA

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74F378 Parallel D-Type Register with Enable
74F378 Parallel D-Type Register with Enable

The 74F378 is a 6-bit register with a buffered common Enable. This device is similar to the 74F174, but with common Enable rather than common Master Reset.
s 6-bit high-speed parallel register s Positive edge-triggered D-type inputs s Fully buffered common clock and enable inputs s Input clamp diodes limit high-speed termination effects s Full TTL and CMOS compatible
Ordering Code:

Order Number Package Number

Package Description
74F378SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F378SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F378PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009526
74F378

Unit Loading/Fan Out

Pin Names

Enable Input Active LOW Data Inputs Clock Pulse Input Active Rising Edge Outputs

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL
20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA

Functional Description

The 74F378 consists of six edge-triggered D-type flip-flops with individual D inputs and Q inputs. The Clock CP and Enable E inputs are common to all flip-flops.

When the E input is LOW, new data is entered into the register on the LOW-to-HIGH transition of the CP input. When the E input is HIGH the register will retain the present data independent of the CP input.

Truth Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Clock Transition

Output Qn

No Change H L

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F378

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output
−0.5V to VCC −0.5V to +5.5V

Current Applied to Output
in LOW State Max
twice the rated IOL mA

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Datasheet ID: 74F378PC 513326