74F374MSAX

74F374MSAX Datasheet

74F374 Octal D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
74F374MSAX	74F374MSAX (pdf)

Related Parts	Information
74F374MSA	74F374MSA
74F374SJX	74F374SJX
74F374SJ	74F374SJ
74F374SC	74F374SC
74F374PC	74F374PC
74F374SCX	74F374SCX

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74F374 Octal D-Type Flip-Flop with 3-STATE Outputs 74F374 Octal D-Type Flip-Flop with 3-STATE Outputs The 74F374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable OE are common to all flipflops. s Edge-triggered D-type inputs s Buffered positive edge-triggered clock s 3-STATE outputs for bus-oriented applications s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number Package Number Package Description 74F374SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F374SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F374MSA MSA20 20-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide 74F374PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009524 74F374 Unit Loading/Fan Out Pin Names CP OE Data Inputs Clock Pulse Input Active Rising Edge 3-STATE Output Enable Input Active LOW 3-STATE Outputs U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 150/40 −3 mA/24 mA 20 mA Functional Description The 74F374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affected the state of the flipflops. Truth Table Inputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = High Impedance = LOW-to-HIGH Clock Transition Internal Register Output On H L Z Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F374 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2 −0.5V to +7.0V −0.5V to +7.0V Input Current Note 2 −30 mA to mA Voltage Applied to Output

PDF Datasheet Preview

74F374 Octal D-Type Flip-Flop with 3-STATE Outputs
74F374 Octal D-Type Flip-Flop with 3-STATE Outputs

The 74F374 is a high-speed, low-power octal D-type flipflop featuring separate D-type inputs for each flip-flop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable OE are common to all flipflops.
s Edge-triggered D-type inputs s Buffered positive edge-triggered clock s 3-STATE outputs for bus-oriented applications s Guaranteed 4000V minimum ESD protection
Ordering Code:

Order Number Package Number

Package Description
74F374SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F374SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F374MSA

MSA20
20-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide
74F374PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009524
74F374

Unit Loading/Fan Out

Pin Names

CP OE

Data Inputs Clock Pulse Input Active Rising Edge 3-STATE Output Enable Input Active LOW 3-STATE Outputs

U.L.

Input IIH/IIL

HIGH/LOW

Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
150/40 −3 mA/24 mA 20 mA

Functional Description

The 74F374 consists of eight edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affected the state of the flipflops.

Truth Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= High Impedance = LOW-to-HIGH Clock Transition

Internal Register

Output On H L Z

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F374

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2
−0.5V to +7.0V −0.5V to +7.0V

Input Current Note 2
−30 mA to mA

Voltage Applied to Output

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Datasheet ID: 74F374MSAX 513324