74F373PC

74F373PC Datasheet

74F373 Octal Transparent Latch with 3-STATE Outputs

Part	Datasheet
74F373PC	74F373PC (pdf)

Related Parts	Information
74F373SJ	74F373SJ
74F373MSA	74F373MSA
74F373MSAX	74F373MSAX
74F373SJX	74F373SJX
74F373SCX	74F373SCX
74F373SC	74F373SC

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74F373 Octal Transparent Latch with 3-STATE Outputs 74F373 Octal Transparent Latch with 3-STATE Outputs The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH the bus output is in the high impedance state. s Eight latches in a single package s 3-STATE outputs for bus interfacing s Guaranteed 4000V minimum ESD protection Ordering Code: Order Number Package Number Package Description 74F373SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74F373SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F373MSA MSA20 20-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide 74F373PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009523 74F373 Unit Loading/Fan Out Pin Names LE OE Data Inputs Latch Enable Input Active HIGH Output Enable Input Active LOW 3-STATE Latch Outputs U.L. HIGH/LOW 150/40 Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA Functional Description Truth Table The 74F373 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable LE input is HIGH, Inputs data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high H = HIGH Voltage Level L = LOW Voltage Level impedance mode but this does not interfere with entering X = Immaterial new data into the latches. Z = High Impedance State Output On H L On no change Z Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F373 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias −55°C to +150°C VCC Pin Potential to Ground Pin Input Voltage Note 2

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74F373 Octal Transparent Latch with 3-STATE Outputs
74F373 Octal Transparent Latch with 3-STATE Outputs

The 74F373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH the bus output is in the high impedance state.
s Eight latches in a single package s 3-STATE outputs for bus interfacing s Guaranteed 4000V minimum ESD protection
Ordering Code:

Order Number Package Number

Package Description
74F373SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74F373SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F373MSA

MSA20
20-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide
74F373PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009523
74F373

Unit Loading/Fan Out

Pin Names

LE OE

Data Inputs Latch Enable Input Active HIGH Output Enable Input Active LOW 3-STATE Latch Outputs

U.L. HIGH/LOW
150/40

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −3 mA/24 mA 20 mA

Functional Description

Truth Table

The 74F373 contains eight D-type latches with 3-STATE output buffers. When the Latch Enable LE input is HIGH,

Inputs
data on the Dn inputs enters the latches. In this condition
the latches are transparent, i.e., a latch output will change
state each time its D input changes. When LE is LOW, the
latches store the information that was present on the D
inputs a setup time preceding the HIGH-to-LOW transition
of LE. The 3-STATE buffers are controlled by the Output

Enable OE input. When OE is LOW, the buffers are in the bi-state mode. When OE is HIGH the buffers are in the high

H = HIGH Voltage Level L = LOW Voltage Level
impedance mode but this does not interfere with entering X = Immaterial
new data into the latches.

Z = High Impedance State

Output

On H L On no change Z

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F373

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias
−55°C to +150°C

VCC Pin Potential to Ground Pin Input Voltage Note 2

More datasheets: S1KB-13 | S1JB-13 | S1GB-13 | S1K-13 | S1A-13 | 74F373SJ | 74F373MSA | 74F373MSAX | 74F373SJX | 74F373SCX

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Datasheet ID: 74F373PC 513323