74F352PC

74F352PC Datasheet

74F352 Dual 4-Input Multiplexer

Part	Datasheet
74F352PC	74F352PC (pdf)

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74F352 Dual 4-Input Multiplexer 74F352 Dual 4-Input Multiplexer The 74F352 is a very high-speed dual 4-input multiplexer with common Select inputs and individual Enable inputs for each section. It can select two bits of data from four sources. The two buffered outputs present data in the inverted complementary form. The 74F352 is the functional equivalent of the 74F153 except with inverted outputs. s Inverted version of 74F153 s Separate enables for each multiplexer s Input clamp diode limits high speed termination effects Ordering Code: Order Number Package Number Package Description 74F352SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F352PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Truth Table Select Inputs Inputs a or b Output S0 S1 E I0 I1 I2 I3 XXHXXXX H L LXXX H L LHXXX L HL LXLXX H HL LXHXX L LHLXXLX H LHLXXHX L HHLXXX L H HHLXXXH L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial 1999 Fairchild Semiconductor Corporation DS009519 74F352 Unit Loading/Fan Out Pin Names Ea Eb Za, Zb Side A Data Inputs Side B Data Inputs Common Select Inputs Side A Enable Input Active LOW Side B Enable Input Active LOW Multiplexer Outputs Inverted U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA Functional Description The 74F352 is a dual 4-input multiplexer. It selects two bits of data from up to four sources under the control of the common Select inputs S0, S1 . The two 4-input multiplexer circuits have individual active LOW Enables Ea, Eb which can be used to strobe the outputs independently. When the Enables Ea, Eb are HIGH, the corresponding outputs Za, Zb are forced HIGH. The logic equations for the outputs are shown below: Za = Ea • I0a • S1 • S0 + I1a • S1• S0 + I2a • S1 • S0 + I3a • S1 • S0 Zb = Eb • I0b • S1 • S0 + I1b • S1• S0 + I2b • S1 • S0 + I3b • S1 • S0 The 74F352 can be used to move data from a group of registers to a common output bus. The particular register from which the data came would be determined by the state of the Select inputs. A less obvious application is as a function generator. The 74F352 can generate two functions of three variables. This is useful for implementing highly irregular random logic. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F352 Absolute Maximum Ratings Note 1 Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Junction Temperature under Bias

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74F352 Dual 4-Input Multiplexer
74F352 Dual 4-Input Multiplexer

The 74F352 is a very high-speed dual 4-input multiplexer with common Select inputs and individual Enable inputs for each section. It can select two bits of data from four sources. The two buffered outputs present data in the inverted complementary form. The 74F352 is the functional equivalent of the 74F153 except with inverted outputs.
s Inverted version of 74F153 s Separate enables for each multiplexer s Input clamp diode limits high speed termination effects
Ordering Code:

Order Number Package Number

Package Description
74F352SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F352PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Truth Table

Select Inputs

Inputs a or b Output

S0 S1 E I0 I1 I2 I3

XXHXXXX H

L LXXX H

L LHXXX L

HL LXLXX H

HL LXHXX L

LHLXXLX H

LHLXXHX L HHLXXX L H

HHLXXXH L

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
1999 Fairchild Semiconductor Corporation DS009519
74F352

Unit Loading/Fan Out

Pin Names

Ea Eb Za, Zb

Side A Data Inputs Side B Data Inputs Common Select Inputs Side A Enable Input Active LOW Side B Enable Input Active LOW Multiplexer Outputs Inverted

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA

Functional Description

The 74F352 is a dual 4-input multiplexer. It selects two bits of data from up to four sources under the control of the common Select inputs S0, S1 . The two 4-input multiplexer circuits have individual active LOW Enables Ea, Eb which can be used to strobe the outputs independently. When the Enables Ea, Eb are HIGH, the corresponding outputs Za, Zb are forced HIGH. The logic equations for the outputs are shown below:

Za = Ea
• I0a
• S1
• S0 + I1a
• S1• S0 +

I2a
• S1
• S0 + I3a
• S1
• S0

Zb = Eb
• I0b
• S1
• S0 + I1b
• S1• S0 +

I2b
• S1
• S0 + I3b
• S1
• S0

The 74F352 can be used to move data from a group of registers to a common output bus. The particular register from which the data came would be determined by the state of the Select inputs. A less obvious application is as a function generator. The 74F352 can generate two functions of three variables. This is useful for implementing highly irregular random logic.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F352

Absolute Maximum Ratings Note 1

Storage Temperature
−65°C to +150°C

Ambient Temperature under Bias
−55°C to +125°C

Junction Temperature under Bias

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Datasheet ID: 74F352PC 513320