74F169SCX

74F169SCX Datasheet

74F169 4-Stage Synchronous Bidirectional Counter

Part	Datasheet
74F169SCX	74F169SCX (pdf)

Related Parts	Information
74F169PC	74F169PC
74F169SJ	74F169SJ
74F169SJX	74F169SJX
74F169SC	74F169SC

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74F169 4-Stage Synchronous Bidirectional Counter 74F169 4-Stage Synchronous Bidirectional Counter The 74F169 is a fully synchronous 4-stage up/down counter. The 74F169 is a modulo-16 binary counter. Features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock. s Asynchronous counting and loading s Built-in lookahead carry capability s Presettable for programmable operation Ordering Code: Order Number Package Number Package Description 74F169SC M16A 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 74F169SJ M16D 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74F169PC N16E 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC 2000 Fairchild Semiconductor Corporation DS009488 74F169 Unit Loading/Fan Out Pin Names CEP CET CP PE U/D TC Count Enable Parallel Input Active LOW Count Enable Trickle Input Active LOW Clock Pulse Input Active Rising Edge Parallel Data Inputs Parallel Enable Input Active LOW Up-Down Count Control Input Flip-Flop Outputs Terminal Count Output Active LOW U.L. HIGH/LOW Input IIH/IIL Output IOH/IOL 20 µA/−0.6 mA 20 µA/−1.2 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA Functional Description The 74F169 uses edge-triggered J-K type flip-flops and has no constraints on changing the control or data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the inputs enters the flip-flops on the next rising edge of the clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH the U/D input then determines the direction of counting. The Terminal Count TC output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 15 for the 74F169 in the Count Up mode. The TC output state is not a function of the Count Enable Parallel CEP input level. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended see logic equations below . Count Enable = CEP • CET • PE Up 74F169 TC = Q0 • Q1 • Q2 • Q3 • Up • CET Down TC = Q0 • Q1 • Q2 • Q3 • Down • CET Mode Select Table PE CEP CET U/D Action on Rising Clock Edge L X Load Pn Qn H L H Count Up Increment H L Count Down Decrement H X No Change Hold H X H X No Change Hold H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial State Diagram 74F169 Logic Diagram Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74F169 Absolute Maximum Ratings Note 1 Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage Note 2 Input Current Note 2 Voltage Applied to Output in HIGH State with VCC = 0V Standard Output 3-STATE Output Current Applied to Output in LOW State Max −65°C to +150°C −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to mA −0.5V to VCC −0.5V to +5.5V twice the rated IOL mA Recommended Operating Conditions Free Air Ambient Temperature Supply Voltage 0°C to +70°C +4.5V to +5.5V

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74F169 4-Stage Synchronous Bidirectional Counter
74F169 4-Stage Synchronous Bidirectional Counter

The 74F169 is a fully synchronous 4-stage up/down counter. The 74F169 is a modulo-16 binary counter. Features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the LOW-to-HIGH transition of the clock.
s Asynchronous counting and loading s Built-in lookahead carry capability s Presettable for programmable operation
Ordering Code:

Order Number Package Number

Package Description
74F169SC

M16A
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow
74F169SJ

M16D
16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74F169PC

N16E
16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC
2000 Fairchild Semiconductor Corporation DS009488
74F169

Unit Loading/Fan Out

Pin Names

CEP CET CP PE U/D TC

Count Enable Parallel Input Active LOW Count Enable Trickle Input Active LOW Clock Pulse Input Active Rising Edge Parallel Data Inputs Parallel Enable Input Active LOW Up-Down Count Control Input Flip-Flop Outputs Terminal Count Output Active LOW

U.L. HIGH/LOW

Input IIH/IIL Output IOH/IOL
20 µA/−0.6 mA 20 µA/−1.2 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA 20 µA/−0.6 mA −1 mA/20 mA −1 mA/20 mA

Functional Description

The 74F169 uses edge-triggered J-K type flip-flops and has no constraints on changing the control or data input signals in either state of the clock. The only requirement is that the various inputs attain the desired state at least a setup time before the rising edge of the clock and remain valid for the recommended hold time thereafter. The parallel load operation takes precedence over other operations, as indicated in the Mode Select Table. When PE is LOW, the data on the inputs enters the flip-flops on the next rising edge of the clock. In order for counting to occur, both CEP and CET must be LOW and PE must be HIGH the U/D input then determines the direction of counting. The Terminal Count TC output is normally HIGH and goes LOW, provided that CET is LOW, when a counter reaches zero in the Count Down mode or reaches 15 for the 74F169 in the Count Up mode. The TC output state is not a function of the Count Enable Parallel CEP input level. Since the TC signal is derived by decoding the flip-flop states, there exists the possibility of decoding spikes on TC. For this reason the use of TC as a clock signal is not recommended see logic equations below .

Count Enable = CEP
• CET
• PE

Up 74F169 TC = Q0
• Q1
• Q2
• Q3
• Up
• CET

Down TC = Q0
• Q1
• Q2
• Q3
• Down
• CET

Mode Select Table

PE CEP CET U/D

Action on Rising Clock Edge

L X Load Pn Qn H L H Count Up Increment

H L Count Down Decrement

H X No Change Hold

H X H X No Change Hold

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

State Diagram
74F169

Logic Diagram

Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74F169

Absolute Maximum Ratings Note 1

Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage Note 2 Input Current Note 2 Voltage Applied to Output
in HIGH State with VCC = 0V Standard Output 3-STATE Output Current Applied to Output in LOW State Max
−65°C to +150°C −55°C to +125°C −55°C to +150°C
−0.5V to +7.0V −0.5V to +7.0V −30 mA to mA
−0.5V to VCC −0.5V to +5.5V
twice the rated IOL mA

Recommended Operating Conditions

Free Air Ambient Temperature Supply Voltage
0°C to +70°C +4.5V to +5.5V

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Datasheet ID: 74F169SCX 513287