74F161APC

74F161APC Datasheet

74F161A, 74F163A Synchronous Presettable Binary Counter

Part	Datasheet
74F161APC	74F161APC (pdf)

Related Parts	Information
74F161ASJX	74F161ASJX
74F161ASC	74F161ASC
74F163ASC	74F163ASC
74F161ASCX	74F161ASCX
74F161ASJ	74F161ASJ
74F163ASJX	74F163ASJX
74F163ASCX	74F163ASCX
74F163ASJ	74F163ASJ
74F163APC	74F163APC

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74F161A, 74F163A Synchronous Presettable Binary Counter 74F161A, 74F163A Synchronous Presettable Binary Counter April 2007 • Synchronous counting and loading • High-speed synchronous expansion • Typical count frequency of 120MHz The 74F161A and 74F163A are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multi-stage counters. The 74F161A has an asynchronous Master-Reset input that overrides all other inputs and forces the outputs LOW. The 74F163A has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. The 74F161A and 74F163A are high-speed versions of the 74F161 and 74F163. Ordering Information Order Number Package Number Package Description 74F161ASC 74F161ASJ 74F161APC 74F163ASC 74F163ASJ 74F163APC M16A M16D N16E M16A M16D N16E 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. Connection Diagrams 74F161A 74F163A 74F161A, 74F163A Synchronous Presettable Binary Counter Logic Symbols 74F161A IEEE/IEC 74F163A IEEE/IEC 74F161A 74F163A Unit Loading/Fan Out Pin Names CEP CET CP MR 74F161A SR 74F163A PE TC Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Active Rising Edge Asynchronous Master Reset Input Active LOW Synchronous Reset Input Active LOW Parallel Data Inputs Parallel Enable Input Active LOW Flip-Flop Outputs Terminal Count Output U.L. HIGH / LOW / / / / / / / 50 / 50 / Input IIH / IIL Output IOH / IOL 20µA / -0.6mA 20µA / -1.2mA 20µA / mA 20µA / mA 20µA / mA 20µA / mA 20µA / -1.2mA -1mA / 20mA -1mA / 20mA 1988 Fairchild Semiconductor Corporation 74F161A, 74F163A Synchronous Presettable Binary Counter Functional Description The 74F161A and 74F163A count in modulo-16 binary sequence. From state 15 HHHH they increment to state 0 LLLL . The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs except due to Master Reset of the 74F161A occur as a result of, and synchronous with, the LOW-toHIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence asynchronous reset 74F161A , synchronous reset 74F163A , parallel load, count-up and hold. Five control Reset MR, 74F161A , Synchronous Reset SR, 74F163A , Parallel Enable PE , Count Enable Parallel CEP and Count Enable Trickle determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data Pn inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR 'F161A or SR 74F163A HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The 74F161A and 74F163A use D-type edge triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. The Terminal Count TC output is HIGH when CET is HIGH and the counter is in state To implement synchronous multi-stage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the 74F568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers. Logic Equations Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET Mode Select Table Action on the Rising SR 1 PE CET CEP Clock Edge X Reset Clear X Load H Count Increment X No Change Hold L No Change Hold H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note For 74F163A only State Diagram 1988 Fairchild Semiconductor Corporation 74F161A, 74F163A Synchronous Presettable Binary Counter Block Diagram Figure 1988 Fairchild Semiconductor Corporation 74F161A, 74F163A Synchronous Presettable Binary Counter Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

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74F161A, 74F163A Synchronous Presettable Binary Counter
74F161A, 74F163A Synchronous Presettable Binary Counter

April 2007
• Synchronous counting and loading
• High-speed synchronous expansion
• Typical count frequency of 120MHz

The 74F161A and 74F163A are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multi-stage counters. The 74F161A has an asynchronous Master-Reset input that overrides all other inputs and forces the outputs LOW. The 74F163A has a Synchronous Reset input that overrides counting and parallel loading and allows the outputs to be simultaneously reset on the rising edge of the clock. The 74F161A and 74F163A are high-speed versions of the 74F161 and 74F163.
Ordering Information

Order Number

Package Number

Package Description
74F161ASC 74F161ASJ 74F161APC 74F163ASC 74F163ASJ 74F163APC

M16A M16D N16E M16A M16D N16E
16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 16-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow 16-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 16-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

Connection Diagrams
74F161A
74F163A
74F161A, 74F163A Synchronous Presettable Binary Counter

Logic Symbols
74F161A IEEE/IEC
74F163A IEEE/IEC
74F161A
74F163A

Unit Loading/Fan Out

Pin Names CEP CET CP MR 74F161A SR 74F163A PE TC

Description Count Enable Parallel Input Count Enable Trickle Input Clock Pulse Input Active Rising Edge Asynchronous Master Reset Input Active LOW Synchronous Reset Input Active LOW Parallel Data Inputs Parallel Enable Input Active LOW Flip-Flop Outputs Terminal Count Output

U.L. HIGH / LOW
/ / / / / / / 50 / 50 /

Input IIH / IIL Output IOH / IOL
20µA / -0.6mA 20µA / -1.2mA 20µA / mA 20µA / mA 20µA / mA 20µA / mA 20µA / -1.2mA -1mA / 20mA -1mA / 20mA
1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Synchronous Presettable Binary Counter

Functional Description

The 74F161A and 74F163A count in modulo-16 binary sequence. From state 15 HHHH they increment to state 0 LLLL . The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs except due to Master Reset of the 74F161A occur as a result of, and synchronous with, the LOW-toHIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence asynchronous reset 74F161A , synchronous reset 74F163A , parallel load, count-up and hold. Five control Reset MR, 74F161A , Synchronous Reset SR, 74F163A , Parallel Enable PE , Count Enable Parallel CEP and Count Enable Trickle determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on SR overrides counting and parallel loading and allows all outputs to go LOW on the next rising edge of CP. A LOW signal on PE overrides counting and allows information on the Parallel Data Pn inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR 'F161A or SR 74F163A HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting.

The 74F161A and 74F163A use D-type edge triggered flip-flops and changing the SR, PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed.

The Terminal Count TC output is HIGH when CET is HIGH and the counter is in state To implement synchronous multi-stage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Please refer to the 74F568 data sheet. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, counters or registers.

Logic Equations Count Enable = CEP
• CET
• PE TC = Q0
• Q1
• Q2
• Q3
• CET

Mode Select Table

Action on the Rising SR 1 PE CET CEP Clock Edge

X Reset Clear

X Load

H Count Increment

X No Change Hold

L No Change Hold

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Note For 74F163A only

State Diagram
1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Synchronous Presettable Binary Counter

Block Diagram

Figure
1988 Fairchild Semiconductor Corporation
74F161A, 74F163A Synchronous Presettable Binary Counter

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

More datasheets: FAN5029MPX | M33519 SL001 | M33519 SL002 | M33519 SL005 | 600684 | 600685 | 74F161ASJX | 74F161ASC | 74F163ASC | 74F161ASCX

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Datasheet ID: 74F161APC 513284