74F1071MTC
74F1071MTC Datasheet
74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device
| Part | Datasheet |
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74F1071MTC |
74F1071MTC (pdf) |
| Related Parts | Information |
|---|---|
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74F1071MTCX |
74F1071MTCX |
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74F1071MSA |
74F1071MSA |
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74F1071SCX |
74F1071SCX |
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74F1071MSAX |
74F1071MSAX |
|
74F1071SC |
74F1071SC |
| PDF Datasheet Preview |
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| 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device January 2008 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device • 18-bit array structure in 20-pin package • Bipolar voltage clamping action • Dual center pin grounds for min inductance • Robust design for ESD protection • Low input capacitance • Optimum voltage clamping for 5V CMOS/TTL The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge ESD . The inputs of the device aggressively clamp voltage excursions nominally at 0.5V below and 7V above ground. Ordering Information Order Number 74F1071SC 74F1071MSA 74F1071MTC Package Number M20B MSA20 MTC20 Package Description 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Shrink Small Outline Package SSOP , JEDEC MO-150, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC J-STD-020B standard. Connection Diagram Note Simplified Component Representation 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TSTG TA TJ VI II Parameter Storage Temperature Ambient Temperature Under Bias Junction Temperature Under Bias Input Voltage 1 Input Current 1 ESD 2 Human Body Model MIL-STD-883D method IEC 801-2 Machine Model EIAJIC-121-1981 DC Latchup Source Current JEDEC Method 17 Package Power Dissipation +70°C SOIC Package Rating to +150°C to +125°C to +150°C to +6V to +50mA ±10kV ±6kV ±2kV ±500mA 800mW Notes Voltage ratings may be exceeded if current ratings and junction temperature and power consumption ratings are not exceeded. ESD Rating for Direct contact discharge using ESD Simulation Tester. Higher rating may be realized in the actual application. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. TA VZ JA SOIC Package SSOP Package Rating 0°C to +70°C 0V to VDC 100°C/W 110°C/W 1994 Fairchild Semiconductor Corporation 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device DC Electrical Characteristics Parameter Conditions IIH Input HIGH Current VIN = 5.25V Untested Input GND VIN = 5.5V Untested Input GND IZ = 1mA Untested Inputs GND IZ = 50mA Untested Inputs GND VF Forward Voltage IF = Untested Inputs 5V IF = Untested Inputs 5V ICT Adjacent Input Crosstalk CIN Input Capacitance VBIAS = 0 VDC small signal 1MHz VBIAS = 5 VDC TA = +25°C Min. Typ. Max. |
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