74ALVCH16374TX

74ALVCH16374TX Datasheet

74ALVCH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold

Part	Datasheet
74ALVCH16374TX	74ALVCH16374TX (pdf)

Related Parts	Information
74ALVCH16374T	74ALVCH16374T

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74ALVCH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold 74ALVCH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold The ALVCH16374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock CP and output enable OE are common to each byte and can be shorted together for full 16-bit operation. The ALVCH16374 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74ALVCH16374 is designed for low voltage 1.65V to 3.6V VCC applications with output compatibility up to 3.6V. The 74ALVCH16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external pull-up/pull-down resistors s tPD ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V Ordering Code: Order Number Package Number Package Descriptions 74ALVCH16374T Note 1 MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Note 1 Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol 2002 Fairchild Semiconductor Corporation DS500627 74ALVCH16374 Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA Top Thru View Pin Descriptions Pin Names OEn CPn NC Output Enable Input Active LOW Clock Pulse Input Bushold Inputs Outputs No Connect FBGA Pin Assignments O0 NC OE1 CP1 NC O1 NC O3 VCC O5 GND I5 O7 GND I7 O10 O9 GND I9 O11 VCC O14 O13 NC O15 NC OE2 CP2 NC Truth Tables Inputs Outputs OE1 L Inputs Outputs OE2 L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, control inputs may not float Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of CP 74ALVCH16374 Functional Description The 74ALVCH16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each Logic Diagram flip-flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CPn transition. With the Output Enable OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops. Byte 1 0:7 Byte 2 8:15 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ALVCH16374 Absolute Maximum Ratings Note 2 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 3 DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK

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74ALVCH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold
74ALVCH16374 Low Voltage 16-Bit D-Type Flip-Flop with Bushold

The ALVCH16374 contains sixteen non-inverting D-type flip-flops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock CP and output enable OE are common to each byte and can be shorted together for full 16-bit operation.

The ALVCH16374 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level.

The 74ALVCH16374 is designed for low voltage 1.65V to 3.6V VCC applications with output compatibility up to 3.6V.

The 74ALVCH16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors s tPD
ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V
Ordering Code:

Order Number

Package Number

Package Descriptions
74ALVCH16374T Note 1

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Note 1 Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol
2002 Fairchild Semiconductor Corporation DS500627
74ALVCH16374

Connection Diagrams

Pin Assignment for TSSOP

Pin Assignment for FBGA Top Thru View

Pin Descriptions

Pin Names

OEn CPn NC

Output Enable Input Active LOW Clock Pulse Input Bushold Inputs Outputs No Connect

FBGA Pin Assignments

O0 NC OE1 CP1 NC

O1 NC

O3 VCC

O5 GND I5

O7 GND I7

O10 O9 GND I9

O11 VCC

O14 O13 NC

O15 NC OE2 CP2 NC

Truth Tables

Inputs

Outputs

OE1 L

Inputs

Outputs

OE2 L

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, control inputs may not float Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of CP
74ALVCH16374

Functional Description

The 74ALVCH16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each

Logic Diagram
flip-flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CPn transition. With the Output Enable OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops.

Byte 1 0:7

Byte 2 8:15

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ALVCH16374

Absolute Maximum Ratings Note 2

Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 3 DC Input Diode Current IIK

VI < 0V DC Output Diode Current IOK

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Datasheet ID: 74ALVCH16374TX 513254