74ALVCH16373TX

74ALVCH16373TX Datasheet

74ALVCH16373 Low Voltage 16-Bit Transparent Latch with Bushold

Part	Datasheet
74ALVCH16373TX	74ALVCH16373TX (pdf)

Related Parts	Information
74ALVCH16373T	74ALVCH16373T

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74ALVCH16373 Low Voltage 16-Bit Transparent Latch with Bushold 74ALVCH16373 Low Voltage 16-Bit Transparent Latch with Bushold The ALVCH16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch Enable LE is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the outputs are in a high impedance state. The ALVCH16373 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74ALVCH16373 is designed for low voltage 1.65V to 3.6V VCC applications with output compatibility up to 3.6V. The 74ALVCH16373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external pull-up/pull-down resistors s tPD In to On ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V Ordering Code: Order Number Package Number Package Description 74ALVCH16373T MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol 2002 Fairchild Semiconductor Corporation DS500631 74ALVCH16373 Connection Diagram Pin Descriptions Pin Names OEn LEn NC Description Output Enable Input Active LOW Latch Enable Input Bushold Inputs Outputs No Connect Truth Tables Inputs Outputs Inputs Outputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, control inputs may not float Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of Latch Enable 74ALVCH16373 Functional Description The 74ALVCH16373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable LEn input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time Logic Diagram its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3-STATE outputs are controlled by the Output Enable OEn input. When OEn is LOW the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ALVCH16373 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 2 DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK VO < 0V DC Output Source/Sink Current IOH/IOL DC VCC or GND Current per Supply Pin ICC or GND Storage Temperature Range TSTG −0.5V to +4.6V −0.5V to 4.6V −0.5V to VCC +0.5V −50 mA −50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions Note 3 Power Supply Operating 1.65V to 3.6V Input Voltage VI Output Voltage VO Free Air Operating Temperature TA Minimum Input Edge Rate 0V to VCC 0V to VCC −40°C to +85°C

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74ALVCH16373 Low Voltage 16-Bit Transparent Latch with Bushold
74ALVCH16373 Low Voltage 16-Bit Transparent Latch with Bushold

The ALVCH16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear to be transparent to the data when the Latch Enable LE is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the outputs are in a high impedance state.

The ALVCH16373 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level.

The 74ALVCH16373 is designed for low voltage 1.65V to 3.6V VCC applications with output compatibility up to 3.6V.

The 74ALVCH16373 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminates the need for external
pull-up/pull-down resistors s tPD In to On
ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V
Ordering Code:

Order Number

Package Number

Package Description
74ALVCH16373T

MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol
2002 Fairchild Semiconductor Corporation DS500631
74ALVCH16373

Connection Diagram

Pin Descriptions

Pin Names

OEn LEn NC

Description Output Enable Input Active LOW

Latch Enable Input Bushold Inputs Outputs No Connect

Truth Tables

Inputs

Outputs

Inputs

Outputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, control inputs may not float Z = High Impedance O0 = Previous O0 before HIGH-to-LOW of Latch Enable
74ALVCH16373

Functional Description

The 74ALVCH16373 contains sixteen edge D-type latches with 3-STATE outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable LEn input is HIGH, data on the In enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time

Logic Diagram
its I input changes. When LEn is LOW, the latches store information that was present on the I inputs a setup time preceding the HIGH-to-LOW transition on LEn. The 3-STATE outputs are controlled by the Output Enable OEn input. When OEn is LOW the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ALVCH16373

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 2 DC Input Diode Current IIK

VI < 0V DC Output Diode Current IOK

VO < 0V DC Output Source/Sink Current

IOH/IOL DC VCC or GND Current per

Supply Pin ICC or GND Storage Temperature Range TSTG
−0.5V to +4.6V −0.5V to 4.6V
−0.5V to VCC +0.5V
−50 mA
−50 mA
±50 mA
±100 mA −65°C to +150°C

Recommended Operating Conditions Note 3

Power Supply

Operating
1.65V to 3.6V

Input Voltage VI Output Voltage VO Free Air Operating Temperature TA Minimum Input Edge Rate
0V to VCC 0V to VCC −40°C to +85°C

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Datasheet ID: 74ALVCH16373TX 513253