74ALVCH16244T
74ALVCH16244T Datasheet
74ALVCH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold
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74ALVCH16244T |
74ALVCH16244T (pdf) |
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74ALVCH16244TX |
74ALVCH16244TX |
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| 74ALVCH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold 74ALVCH16244 Low Voltage 16-Bit Buffer/Line Driver with Bushold The ALVCH16244 contains sixteen non-inverting buffers with 3-STATE outputs to be employed as a memory and address driver, clock driver, or bus oriented transmitter/ receiver. The device is nibble 4-bit controlled. Each nibble has separate 3-STATE control inputs which can be shorted together for full 16-bit operation. The ALVCH16244 data inputs include active bushold circuitry, eliminating the need for external pull-up resistors to hold unused or floating data inputs at a valid logic level. The 74ALVCH16244 is designed for low voltage 1.65V to 3.6V VCC applications with output capability up to 3.6V. The 74ALVCH16244 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s 1.65V to 3.6V VCC supply operation s 3.6V tolerant control inputs and outputs s Bushold on data inputs eliminating the need for external pull-up/pull-down resistors s tPD 3 ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Uses patented noise/EMI reduction circuitry s Latch-up conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model > 200V Ordering Code: Order Number Package Number Package Description 74ALVCH16244T MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol Pin Descriptions Pin Names Description Output Enable Input Active LOW Bushold Inputs Outputs 2002 Fairchild Semiconductor Corporation DS500625 74ALVCH16244 Connection Diagram Truth Tables Inputs Inputs OE3 L H I8-I11 L H X Outputs Outputs Inputs I4-I7 Outputs O4-O7 L H Z Functional Description The 74ALVCH16244 contains sixteen non-inverting buffers with 3-STATE outputs. The device is nibble 4 bits controlled with each nibble functioning identically, but independent of each other. The control pins may be shorted together to obtain full 16-bit operation.The 3-STATE out- Logic Diagram Inputs Outputs I12-I15 O12-O15 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance puts are controlled by an Output Enable OEn input. When OEn is LOW, the outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the inputs. 74ALVCH16244 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 2 DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK VO < 0V DC Output Source/Sink Current IOH/IOL DC VCC or GND Current per Supply Pin ICC or GND Storage Temperature Range TSTG −0.5V to +4.6V −0.5V to 4.6V −0.5V to VCC +0.5V −50 mA −50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions Note 3 |
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