74ALVC16501MTDX

74ALVC16501MTDX Datasheet

74ALVC16501 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

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74ALVC16501MTDX	74ALVC16501MTDX (pdf)

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74ALVC16501MTD	74ALVC16501MTD

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74ALVC16501 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs 74ALVC16501 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs The ALVC16501 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable LEAB and LEBA , and clock CLKAB and CLKBA inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in a highimpedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary OEAB is active HIGH and OEBA is active LOW . The ALVC16501 is designed for low voltage 1.65V to 3.6V VCC applications with I/O capability up to 3.6V. The ALVC16501 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s VCC supply operation s 3.6V tolerant inputs and outputs s tPD A to B, B to A ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model >200V Note 1 To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistor the minimum value of the resistors is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Description 74ALVC16501MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. 2001 Fairchild Semiconductor Corporation DS500683 74ALVC16501 Connection Diagram Pin Descriptions Pin Names OEAB Output Enable Input for A to B Direction Active HIGH OEBA Output Enable Input for B to A Direction Active LOW LEAB, LEBA Latch Enable Inputs CLKAB, CLKBA Clock Inputs Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs Function Table Note 2 Inputs Outputs OEAB LEAB CLKAB An B0 Note 3 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance B0 Note 4 Note 2 A-to-B data flow is shown B-to-A flow is similar but uses OEBA, LEBA and CLKBA. OEBA is active LOW. Note 3 Output level before the indicated steady-state input conditions were established. Note 4 Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW. 74ALVC16501 Logic Diagram 74ALVC16501 Absolute Maximum Ratings Note 5 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 6 DC Input Diode Current IIK VI < 0V DC Output Diode Current IOK VO < 0V DC Output Source/Sink Current IOH/IOL DC VCC or GND Current per Supply Pin ICC or GND Storage Temperature Range TSTG −0.5V to +4.6V −0.5V to 4.6V −0.5V to VCC +0.5V −50 mA −50 mA ±50 mA ±100 mA −65°C to +150°C Recommended Operating Conditions Note 7 Power Supply

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74ALVC16501 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs
74ALVC16501 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs

The ALVC16501 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable LEAB and LEBA , and clock CLKAB and CLKBA inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in a highimpedance state.

Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary OEAB is active HIGH and OEBA is active LOW .

The ALVC16501 is designed for low voltage 1.65V to 3.6V VCC applications with I/O capability up to 3.6V.

The ALVC16501 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s VCC supply operation s 3.6V tolerant inputs and outputs s tPD A to B, B to A
ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal Note 1 s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance Human body model > 2000V Machine model >200V

Note 1 To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistor the minimum value of the resistors is determined by the current-sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Description
74ALVC16501MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
2001 Fairchild Semiconductor Corporation DS500683
74ALVC16501

Connection Diagram

Pin Descriptions

Pin Names

OEAB

Output Enable Input for A to B Direction Active HIGH

OEBA

Output Enable Input for B to A Direction Active LOW

LEAB, LEBA Latch Enable Inputs

CLKAB, CLKBA

Clock Inputs

Side A Inputs or 3-STATE Outputs Side B Inputs or 3-STATE Outputs

Function Table Note 2

Inputs

Outputs

OEAB LEAB CLKAB An

B0 Note 3

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial HIGH or LOW, inputs may not float Z = High Impedance

B0 Note 4

Note 2 A-to-B data flow is shown B-to-A flow is similar but uses OEBA, LEBA and CLKBA. OEBA is active LOW.

Note 3 Output level before the indicated steady-state input conditions were established.

Note 4 Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
74ALVC16501

Logic Diagram
74ALVC16501

Absolute Maximum Ratings Note 5

Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 6 DC Input Diode Current IIK

VI < 0V DC Output Diode Current IOK

VO < 0V DC Output Source/Sink Current

IOH/IOL DC VCC or GND Current per

Supply Pin ICC or GND Storage Temperature Range TSTG
−0.5V to +4.6V −0.5V to 4.6V
−0.5V to VCC +0.5V
−50 mA
−50 mA
±50 mA
±100 mA −65°C to +150°C

Recommended Operating Conditions Note 7

Power Supply

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Datasheet ID: 74ALVC16501MTDX 513237