74ALVC16374MTD

74ALVC16374MTD Datasheet

74ALVC16374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs

Part	Datasheet
74ALVC16374MTD	74ALVC16374MTD (pdf)

Related Parts	Information
74ALVC16374MTDX	74ALVC16374MTDX
74ALVC16374GX	74ALVC16374GX
74ALVC16374G	74ALVC16374G

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74ALVC16374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs 74ALVC16374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs The ALVC16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock CP and output enable OE are common to each byte and can be shorted together for full 16-bit operation. The 74ALVC16374 is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V. The 74ALVC16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation. s 1.65V - 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal Note 1 s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance Human body model ! 2000V Machine model ! 200V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver. Ordering Code: Order Number Package Number Package Descriptions 74ALVC16374GX Note 2 BGA54A 54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide [TAPE and REEL] 74ALVC16374MTD Note 3 MTD48 48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Note 2 BGA package available in Tape and Reel only. Note 3 Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. 2005 Fairchild Semiconductor Corporation DS500692 74ALVC16374 Logic Symbol Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA Top Thru View Pin Descriptions Pin Names OEn CPn NC Description Output Enable Input Active LOW Clock Pulse Input Inputs Outputs No Connect FBGA Pin Assignments O0 NC OE1 CP1 NC O5 GND I5 O7 GND I7 O10 O9 GND I9 O12 O11 VCC O14 O13 NC O15 NC OE2 CP2 NC Truth Tables Inputs Outputs OE1 L Inputs OE2 L H HIGH Voltage Level L LOW Voltage Level X Immaterial HIGH or LOW, inputs may not float Z High Impedance O0 Previous O0 before HIGH-to-LOW of CP Outputs H L O0 Z 74ALVC16374 Functional Description The 74ALVC16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each Logic Diagram flip-flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CPn transition. With the Output Enable OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops. Byte 1 0:7 Byte 2 8:15 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ALVC16374 Absolute Maximum Ratings Note 4 Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 5 DC Input Diode Current IIK VI 0V DC Output Diode Current IOK VO 0V DC Output Source/Sink Current IOH/IOL DC VCC or GND Current per

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74ALVC16374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs
74ALVC16374 Low Voltage 16-Bit D-Type Flip-Flop with 3.6V Tolerant Inputs and Outputs

The ALVC16374 contains sixteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock CP and output enable OE are common to each byte and can be shorted together for full 16-bit operation.

The 74ALVC16374 is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V.

The 74ALVC16374 is fabricated with an advanced CMOS technology to achieve high speed operation while maintaining low CMOS power dissipation.
s 1.65V - 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD
ns max for 3.0V to 3.6V VCC ns max for 2.3V to 2.7V VCC ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion and withdrawal Note 1 s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance Human body model ! 2000V Machine model ! 200V s Also packaged in plastic Fine-Pitch Ball Grid Array FBGA

Note 1 To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Ordering Code:

Order Number Package Number

Package Descriptions
74ALVC16374GX Note 2

BGA54A
54-Ball Fine-Pitch Ball Grid Array FBGA , JEDEC MO-205, 5.5mm Wide [TAPE and REEL]
74ALVC16374MTD Note 3

MTD48
48-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Note 2 BGA package available in Tape and Reel only. Note 3 Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
2005 Fairchild Semiconductor Corporation DS500692
74ALVC16374

Logic Symbol Connection Diagrams

Pin Assignment for TSSOP

Pin Assignment for FBGA Top Thru View

Pin Descriptions

Pin Names

OEn CPn NC

Description Output Enable Input Active LOW Clock Pulse Input Inputs Outputs No Connect

FBGA Pin Assignments

O0 NC OE1 CP1 NC

O5 GND I5

O7 GND I7

O10 O9 GND I9

O12 O11 VCC

O14 O13 NC

O15 NC OE2 CP2 NC

Truth Tables

Inputs

Outputs

OE1 L

Inputs

OE2 L

H HIGH Voltage Level L LOW Voltage Level X Immaterial HIGH or LOW, inputs may not float Z High Impedance O0 Previous O0 before HIGH-to-LOW of CP

Outputs

H L O0 Z
74ALVC16374

Functional Description

The 74ALVC16374 consists of sixteen edge-triggered flip-flops with individual D-type inputs and 3-STATE true outputs. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. Each clock has a buffered clock and buffered Output Enable common to all flip-flops within that byte. The description which follows applies to each byte. Each

Logic Diagram
flip-flop will store the state of their individual I inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CPn transition. With the Output Enable OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the high impedance state. Operations of the OEn input does not affect the state of the flip-flops.

Byte 1 0:7

Byte 2 8:15

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ALVC16374

Absolute Maximum Ratings Note 4

Supply Voltage VCC DC Input Voltage VI Output Voltage VO Note 5 DC Input Diode Current IIK

VI 0V DC Output Diode Current IOK

VO 0V DC Output Source/Sink Current

IOH/IOL DC VCC or GND Current per

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Datasheet ID: 74ALVC16374MTD 513235