74ACTQ843SC

74ACTQ843SC Datasheet

74ACTQ843 Quiet 9-Bit Transparent Latch with 3-STATE Outputs

Part	Datasheet
74ACTQ843SC	74ACTQ843SC (pdf)

Related Parts	Information
74ACTQ843SPC	74ACTQ843SPC
74ACTQ843SCX	74ACTQ843SCX

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74ACTQ843 Quiet 9-Bit Transparent Latch with 3-STATE Outputs 74ACTQ843 Quiet 9-Bit Transparent Latch with 3-STATE Outputs The ACTQ843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths. The ACTQ843 utilizes Fairchild FACT Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features output control and undershoot corrector in addition to a split ground bus for superior performance. s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Inputs and outputs on opposite sides of package for easy interface with microprocessors s Improved latch-up immunity s Outputs source/sink 24 mA s 3-STATE outputs for bus interfacing s TTL compatible inputs Ordering Code: Order Number Package Number Package Description 74ACTQ843SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACTQ843SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram Pin Descriptions Pin Names OE LE CLR PRE Description Data Inputs Data Outputs Output Enable Latch Enable Clear Preset Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS010689 74ACTQ843 Functional Description The ACTQ843 consists of nine D-type latches with 3STATE outputs. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the high impedance state. In addition to the LE and OE pins, the ACTQ843 has a Clear CLR pin and a Preset PRE pin. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. When PRE is LOW, the outputs are HIGH if OE is LOW. Preset overrides CLR. Logic Diagram Function Table Inputs Internal Outputs CLR PRE OE LE D Function H HHL High Z H HHH H High Z H L X NC Latched H LHL Transparent H LHH H H Transparent H L X NC Latched H L LXX H Preset L H LXX Clear L LXX H Preset L H HLX Z Clear/High Z H L HLX H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Z Preset/High Z 74ACTQ843

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74ACTQ843 Quiet 9-Bit Transparent Latch with 3-STATE Outputs
74ACTQ843

Quiet 9-Bit Transparent Latch with 3-STATE Outputs

The ACTQ843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths. The ACTQ843 utilizes Fairchild FACT Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features output control and undershoot corrector in addition to a split ground bus for superior performance.
s Guaranteed simultaneous switching noise level and dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance s Inputs and outputs on opposite sides of package for
easy interface with microprocessors s Improved latch-up immunity s Outputs source/sink 24 mA s 3-STATE outputs for bus interfacing s TTL compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74ACTQ843SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACTQ843SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

Pin Descriptions

Pin Names OE LE CLR PRE

Description Data Inputs Data Outputs Output Enable Latch Enable Clear Preset

Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation.
2000 Fairchild Semiconductor Corporation DS010689
74ACTQ843

Functional Description

The ACTQ843 consists of nine D-type latches with 3STATE outputs. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the high impedance state. In addition to the LE and OE pins, the ACTQ843 has a Clear CLR pin and a Preset PRE pin. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. When PRE is LOW, the outputs are HIGH if OE is LOW. Preset overrides CLR.

Logic Diagram

Function Table

Inputs

Internal Outputs

CLR PRE OE LE D

Function

H HHL

High Z

H HHH H

High Z

H L X NC

Latched

H LHL

Transparent

H LHH H

H Transparent

H L X NC

Latched

H L LXX H

Preset

L H LXX

Clear

L LXX H

Preset

L H HLX

Z Clear/High Z

H L HLX H

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change

Z Preset/High Z
74ACTQ843

More datasheets: MBR1640 | U86-D1627-10121 | 3335 | CC22-230 | 65-54757 | 65-54748 | 65-54756 | 1665 | 74ACTQ843SPC | 74ACTQ843SCX

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Datasheet ID: 74ACTQ843SC 513223