74ACTQ823SCX

74ACTQ823SCX Datasheet

74ACTQ823 Quiet 9-Bit D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
74ACTQ823SCX	74ACTQ823SCX (pdf)

Related Parts	Information
74ACTQ823SPC	74ACTQ823SPC

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74ACTQ823 Quiet 9-Bit D-Type Flip-Flop with 3-STATE Outputs 74ACTQ823 Quiet 9-Bit D-Type Flip-Flop with 3-STATE Outputs The ACTQ823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. The ACTQ823 utilizes Fairchild Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet features output control and undershoot corrector in addition to a split ground bus for superior performance. s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Inputs and outputs on opposite sides of package allow easy interface with microprocessors s Improved latch-up immunity s TTL compatible inputs Ordering Code: Order Number Package Number Package Description 74ACTQ823SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACTQ823SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names OE CLR CP EN Description Data Inputs Data Outputs Output Enable Clear Clock Input Clock Enable Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS010921 74ACTQ823 Functional Description The ACTQ823 consists of nine D-type edge-triggered flipflops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The buffered clock CP and buffered Output Enable OE are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. In addition to the Clock and Output Enable pins, there are Clear CLR and Clock Enable EN pins. These devices are ideal for parity bus interfacing in high performance systems. When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions. Function Table Inputs X L H L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = High Impedance = LOW-to-HIGH Transition NC = No Change Internal Q L H L NC L H L H Output O Z L Z NC Z L H Function High Z High Z Clear Hold Load Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACTQ823 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-Up Source or Sink Current Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65°C to +150°C ± 300 mA

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74ACTQ823 Quiet 9-Bit D-Type Flip-Flop with 3-STATE Outputs
74ACTQ823

Quiet 9-Bit D-Type Flip-Flop with 3-STATE Outputs

The ACTQ823 is a 9-bit buffered register. It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems. The ACTQ823 utilizes Fairchild Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet features output control and undershoot corrector in addition to a split ground bus for superior performance.
s Guaranteed simultaneous switching noise level and dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors s Improved latch-up immunity s TTL compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74ACTQ823SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACTQ823SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names OE CLR CP EN

Description Data Inputs Data Outputs Output Enable Clear Clock Input Clock Enable

Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation.
2000 Fairchild Semiconductor Corporation DS010921
74ACTQ823

Functional Description

The ACTQ823 consists of nine D-type edge-triggered flipflops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The buffered clock CP and buffered Output Enable OE are common to all flip-flops. The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition. With OE LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. In addition to the Clock and Output

Enable pins, there are Clear CLR and Clock Enable EN pins. These devices are ideal for parity bus interfacing in high performance systems.

When CLR is LOW and OE is LOW, the outputs are LOW. When CLR is HIGH, data can be entered into the flip-flops. When EN is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the EN is HIGH, the outputs do not change state, regardless of the data or clock input transitions.

Function Table

Inputs

X L H L H

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= High Impedance = LOW-to-HIGH Transition NC = No Change

Internal

Q L H L NC L H L H

Output

O Z L Z NC Z L H

Function

High Z High Z Clear Hold Load

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACTQ823

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-Up Source
or Sink Current

Junction Temperature TJ PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
± 50 mA
± 50 mA −65°C to +150°C
± 300 mA

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Datasheet ID: 74ACTQ823SCX 513220