74ACTQ74SJ

74ACTQ74SJ Datasheet

74ACTQ74 Quiet Series Dual D-Type

Part	Datasheet
74ACTQ74SJ	74ACTQ74SJ (pdf)

Related Parts	Information
74ACTQ74SCX	74ACTQ74SCX
74ACTQ74PC	74ACTQ74PC
74ACTQ74SJX	74ACTQ74SJX
74ACTQ74SC	74ACTQ74SC

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74ACTQ74 Quiet Series Dual D-Type 74ACTQ74 Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop The 74ACTQ74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. The ACTQ74 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet features output control and undershoot corrector in addition to a split ground bus for superior performance. Asynchronous Inputs LOW input to SD Set sets Q to HIGH level LOW input to CD Clear sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH s ICC reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s 4 kV minimum ESD immunity s TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACTQ74SC 74ACTQ74SJ 74ACTQ74PC M14A M14D N14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form. Connection Diagram Pin Descriptions Pin Names D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2 Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS010920 74ACTQ74 Truth Table Each Half Inputs Outputs H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Clock Transition Q0 = Previous Q before LOW-to-HIGH Transition of Clock Logic Symbols IEEE/IEC Block Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACTQ74 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-Up Source or Sink Current Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65°C to +150°C ± 300 mA 140°C Recommended Operating Conditions Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate VIN from 0.8V to 2.0V VCC 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specifications. DC Electrical Characteristics Parameter Minimum HIGH Level

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74ACTQ74 Quiet Series Dual D-Type
74ACTQ74 Quiet Series Dual D-Type Positive Edge-Triggered Flip-Flop

The 74ACTQ74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary Q, Q outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input.

The ACTQ74 utilizes Fairchild Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet features output control and undershoot corrector in addition to a split ground bus for superior performance.

Asynchronous Inputs LOW input to SD Set sets Q to HIGH level LOW input to CD Clear sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH
s ICC reduced by 50% s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s 4 kV minimum ESD immunity s TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74ACTQ74SC 74ACTQ74SJ 74ACTQ74PC

M14A M14D N14A
14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-120, Narrow 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering form.

Connection Diagram

Pin Descriptions

Pin Names D1, D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2

Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs

FACT Quiet and are trademarks of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS010920
74ACTQ74

Truth Table

Each Half

Inputs

Outputs

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Clock Transition Q0 = Previous Q before LOW-to-HIGH Transition of Clock

Logic Symbols

IEEE/IEC

Block Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACTQ74

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-Up Source or Sink Current

Junction Temperature TJ PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
± 50 mA
± 50 mA −65°C to +150°C
± 300 mA 140°C

Recommended Operating Conditions

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate

VIN from 0.8V to 2.0V VCC 4.5V, 5.5V
4.5V to 5.5V 0V to VCC 0V to VCC
−40°C to +85°C
125 mV/ns

Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of circuits outside databook specifications.

DC Electrical Characteristics

Parameter

Minimum HIGH Level

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Datasheet ID: 74ACTQ74SJ 513218