74ACTQ533MTCX

74ACTQ533MTCX Datasheet

74ACTQ533 Quiet Series Octal Transparent Latch with 3-STATE Outputs

Part	Datasheet
74ACTQ533MTCX	74ACTQ533MTCX (pdf)

Related Parts	Information
74ACTQ533PC	74ACTQ533PC
74ACTQ533SC	74ACTQ533SC
74ACTQ533SCX	74ACTQ533SCX

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74ACTQ533 Quiet Series Octal Transparent Latch with 3-STATE Outputs 74ACTQ533 Quiet Series Octal Transparent Latch with 3-STATE Outputs The ACTQ533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the high impedance state. The ACTQ533 utilizes Fairchild Quiet technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features output control and undershoot corrector in addition to a split ground bus for superior performance. s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch up immunity s Eight latches in a single package s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs source/sink 24 mA s Inverted version of the ACTQ373 s 4 kV minimum ESD immunity Ordering Code: Order Number Package Number Package Description 74ACTQ533SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body 74ACTQ533MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACTQ533PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS010630 74ACTQ533 Truth Table Inputs H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Outputs On Z H L O0 Functional Description The ACTQ533 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable OE input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACTQ533 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = − 0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = − 0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG DC Latchup Source or Sink Current Junction Temperature TJ PDIP − 0.5V to + 7.0V − 20 mA + 20 mA −0.5V to VCC + 0.5V − 20 mA + 20 mA − 0.5V to VCC + 0.5V ± 50 mA ± 50 mA − 65°C to + 150°C ± 300 mA 140°C Recommended Operating Conditions Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate VIN from 0.8V to 2.0V VCC 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns

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74ACTQ533 Quiet Series Octal Transparent Latch with 3-STATE Outputs
74ACTQ533 Quiet Series Octal Transparent Latch with 3-STATE Outputs

The ACTQ533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. When LE is LOW, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the high impedance state.

The ACTQ533 utilizes Fairchild Quiet technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features output control and undershoot corrector in addition to a split ground bus for superior performance.
s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch up immunity s Eight latches in a single package s 3-STATE outputs drive bus lines or buffer memory
address registers s Outputs source/sink 24 mA s Inverted version of the ACTQ373 s 4 kV minimum ESD immunity
Ordering Code:

Order Number Package Number

Package Description
74ACTQ533SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
74ACTQ533MTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACTQ533PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names

Data Inputs Latch Enable Input

Output Enable Input
3-STATE Latch Outputs

FACT Quiet and are trademarks of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS010630
74ACTQ533

Truth Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable

Outputs On Z H L O0

Functional Description

The ACTQ533 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW
transition of LE. The 3-STATE standard outputs are controlled by the Output Enable OE input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACTQ533

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = − 0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = − 0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG DC Latchup Source
or Sink Current

Junction Temperature TJ PDIP
− 0.5V to + 7.0V
− 20 mA + 20 mA −0.5V to VCC + 0.5V
− 20 mA + 20 mA − 0.5V to VCC + 0.5V
± 50 mA
± 50 mA − 65°C to + 150°C
± 300 mA
140°C

Recommended Operating Conditions

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate

VIN from 0.8V to 2.0V VCC 4.5V, 5.5V
4.5V to 5.5V
0V to VCC 0V to VCC −40°C to +85°C 125 mV/ns

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Datasheet ID: 74ACTQ533MTCX 513213