74ACT843SPC

74ACT843SPC Datasheet

74ACT843 9-Bit Transparent Latch

Part	Datasheet
74ACT843SPC	74ACT843SPC (pdf)

Related Parts	Information
74ACT843SCX	74ACT843SCX
74ACT843SC	74ACT843SC

PDF Datasheet Preview
74ACT843 9-Bit Transparent Latch 74ACT843 9-Bit Transparent Latch The ACT843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths. s TTL compatible inputs s 3-STATE outputs for bus interfacing Ordering Code: Order Number Package Number Package Description 74ACT843SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACT843SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. SPC not available in Tape and Reel. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names OE LE CLR PRE Description Data Inputs Data Outputs Output Enable Latch Enable Clear Preset is a trademark of Fairchild Semiconductor Corporation 2000 Fairchild Semiconductor Corporation DS009800 74ACT843 Functional Description The ACT843 consists of nine D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the high impedance state. In addition to Function Tables the LE and OE pins, the ACT843 has a Clear CLR pin and a Preset PRE pin. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. When PRE is LOW, the outputs are HIGH if OE is LOW. Preset overrides CLR. Inputs CLR PRE OE LE H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change Internal Q L H NC L H NC H L H L H Outputs O Z L H NC H L H Z Function High Z High Z Latched Transparent Latched Preset Clear Preset Clear/High Z Preset/High Z Logic Diagram 74ACT843 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC +0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC +0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC +0.5V −20 mA +20 mA −0.5V to VCC +0.5V ±50 mA ±50 mA −65°C to +150°C 140°C Recommended Operating Conditions Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate VIN from 0.8V to 2.0V VCC 4.5V, 5.5V 4.5V to 5.5V

PDF Datasheet Preview

74ACT843 9-Bit Transparent Latch
74ACT843 9-Bit Transparent Latch

The ACT843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths.
s TTL compatible inputs s 3-STATE outputs for bus interfacing
Ordering Code:

Order Number Package Number

Package Description
74ACT843SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACT843SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. SPC not available in Tape and Reel.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names OE LE CLR PRE

Description Data Inputs Data Outputs Output Enable Latch Enable Clear Preset
is a trademark of Fairchild Semiconductor Corporation
2000 Fairchild Semiconductor Corporation DS009800
74ACT843

Functional Description

The ACT843 consists of nine D-type latches with 3-STATE outputs. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the high impedance state. In addition to

Function Tables
the LE and OE pins, the ACT843 has a Clear CLR pin and a Preset PRE pin. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. When PRE is LOW, the outputs are HIGH if OE is LOW. Preset overrides CLR.

Inputs

CLR PRE OE LE

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance NC = No Change

Internal

Q L H NC L H NC H L H L H

Outputs

O Z L H NC H L H Z

Function

High Z High Z Latched Transparent Latched Preset Clear Preset Clear/High Z Preset/High Z

Logic Diagram
74ACT843

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC +0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC +0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ

PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC +0.5V
−20 mA +20 mA −0.5V to VCC +0.5V
±50 mA
±50 mA −65°C to +150°C
140°C

Recommended Operating Conditions

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate

VIN from 0.8V to 2.0V VCC 4.5V, 5.5V
4.5V to 5.5V

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Datasheet ID: 74ACT843SPC 513186