74ACT533SCX

74ACT533SCX Datasheet

74ACT533 Octal Transparent Latch with 3-STATE Outputs

Part	Datasheet
74ACT533SCX	74ACT533SCX (pdf)

Related Parts	Information
74ACT533SC	74ACT533SC
74ACT533PC	74ACT533PC
74ACT533MTC	74ACT533MTC
74ACT533MTCX	74ACT533MTCX

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74ACT533 Octal Transparent Latch with 3-STATE Outputs 74ACT533 Octal Transparent Latch with 3-STATE Outputs The ACT533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the high impedance state. s ICC and IOZ reduced by 50% s Eight latches in a single package s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs source/sink 24 mA s Inverted version of the ACT373 s TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACT533SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACT533MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT533PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs is a trademark of Fairchild Semiconductor Corporation. 2005 Fairchild Semiconductor Corporation DS500311 74ACT533 Functional Description The ACT533 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable OE input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Truth Table Inputs Outputs H HIGH Voltage Level L LOW Voltage Level Z High Impedance X Immaterial O0 Previous O0 before HIGH-to-LOW transition of Latch Enable Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACT533 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI 0.5V VI VCC 0.5V DC Input Voltage VI DC Output Diode Current IOK VO 0.5V VO VCC 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG DC Latchup Source or Sink Current Junction Temperature TJ PDIP 0.5V to 7.0V 20 mA 20 mA to VCC 0.5V 20 mA 20 mA 0.5V to VCC 0.5V r 50 mA r 50 mA 65qC to 150qC r 300 mA 140qC Recommended Operating Conditions Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate 'V/'t VIN from 0.8V to 2.0V VCC 4.5V, 5.5V 4.5V to 5.5V 0V to VCC 0V to VCC 125 mV/ns

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74ACT533 Octal Transparent Latch with 3-STATE Outputs
74ACT533 Octal Transparent Latch with 3-STATE Outputs

The ACT533 consists of eight latches with 3-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable LE is HIGH. When LE is low, the data satisfying the input timing requirements is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the high impedance state.
s ICC and IOZ reduced by 50% s Eight latches in a single package s 3-STATE outputs drive bus lines or buffer memory
address registers s Outputs source/sink 24 mA s Inverted version of the ACT373 s TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74ACT533SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACT533MTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACT533PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names

Data Inputs Latch Enable Input

Output Enable Input
3-STATE Latch Outputs
is a trademark of Fairchild Semiconductor Corporation. 2005 Fairchild Semiconductor Corporation DS500311
74ACT533

Functional Description

The ACT533 contains eight D-type latches with 3-STATE standard outputs. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs at setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable OE input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.

Logic Diagram

Truth Table

Inputs

Outputs

H HIGH Voltage Level

L LOW Voltage Level Z High Impedance X Immaterial

O0 Previous O0 before HIGH-to-LOW transition of Latch Enable

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACT533

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI 0.5V VI VCC 0.5V DC Input Voltage VI DC Output Diode Current IOK VO 0.5V VO VCC 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG DC Latchup Source
or Sink Current

Junction Temperature TJ PDIP
0.5V to 7.0V
20 mA 20 mA to VCC 0.5V
20 mA 20 mA 0.5V to VCC 0.5V
r 50 mA
r 50 mA 65qC to 150qC
r 300 mA
140qC

Recommended Operating Conditions

Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate 'V/'t

VIN from 0.8V to 2.0V VCC 4.5V, 5.5V
4.5V to 5.5V 0V to VCC 0V to VCC
125 mV/ns

More datasheets: DK200P | DK197P | DK199P | DK196P | DK198P | DKBLE | A000007 | BMA223 | 74ACT533SC | 74ACT533PC

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Datasheet ID: 74ACT533SCX 513174