74ACT323PC

74ACT323PC Datasheet

74ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins

Part	Datasheet
74ACT323PC	74ACT323PC (pdf)

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74ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins 74ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins The ACT323 is an 8-bit universal shift/storage register with 3-STATE outputs. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial inputs and outputs are provided for Q0 and Q7 to allow easy cascading. Four operation modes are possible hold store , shift left, shift right and parallel load. s ICC and IOZ reduced by 50% s Common parallel I/O for reduced pin count s Additional serial inputs and outputs for expansion s Four operating modes shift left, shift right, load and store s 3-STATE outputs for bus-oriented applications s Outputs source/sink 24 mA s TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACT323PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram Pin Assignment for DIP FACT is a trademark of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS009787.prf Pin Descriptions Pin Name Clock Pulse Input DS0 DS7 S0, S1 SR Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Synchronous Reset Input OE1, OE2 3-STATE Output Enable Inputs Multiplexed Parallel Data Inputs or 3-STATE Parallel Data Outputs Q0, Q7 Serial Outputs 74ACT323 Functional Description The ACT323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All Mode Select Table other state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, load, hold and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Clock Transition Inputs Response Synchronous Reset = LOW Parallel Load Shift Right etc. Shift Left etc. X Hold 74ACT323 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACT323 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current Per Output Pin ICC or IGND Storage Temperature TSTG −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to V CC + 0.5V

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74ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins
74ACT323 8-Bit Universal Shift/Storage Register with Synchronous Reset and Common I/O Pins

The ACT323 is an 8-bit universal shift/storage register with 3-STATE outputs. Parallel load inputs and flip-flop outputs are multiplexed to minimize pin count. Separate serial inputs and outputs are provided for Q0 and Q7 to allow easy cascading. Four operation modes are possible hold store , shift left, shift right and parallel load.
s ICC and IOZ reduced by 50% s Common parallel I/O for reduced pin count s Additional serial inputs and outputs for expansion s Four operating modes shift left, shift right, load and
store s 3-STATE outputs for bus-oriented applications s Outputs source/sink 24 mA s TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74ACT323PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

Pin Assignment for DIP

FACT is a trademark of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS009787.prf

Pin Descriptions

Pin Name

Clock Pulse Input

DS0 DS7 S0, S1 SR

Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Synchronous Reset Input

OE1, OE2
3-STATE Output Enable Inputs Multiplexed Parallel Data Inputs or
3-STATE Parallel Data Outputs

Q0, Q7

Serial Outputs
74ACT323

Functional Description

The ACT323 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous reset, shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1 as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words.

A LOW signal on SR overrides the Select inputs and allows the flip-flops to be reset by the next rising edge of CP. All

Mode Select Table
other state changes are also initiated by the LOW-to-HIGH CP transition. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed.

A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, load, hold and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation.

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Clock Transition

Inputs

Response

Synchronous Reset = LOW Parallel Load Shift Right etc. Shift Left etc.

X Hold
74ACT323

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACT323

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or

Sink Current IO DC VCC or Ground Current

Per Output Pin ICC or IGND Storage Temperature TSTG
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to V CC + 0.5V

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Datasheet ID: 74ACT323PC 513173