74ACT299MTC

74ACT299MTC Datasheet

74AC299<br>• 74ACT299 8-Input Universal Shift/Storage Register

Part	Datasheet
74ACT299MTC	74ACT299MTC (pdf)

Related Parts	Information
74ACT299PC	74ACT299PC
74ACT299SC	74ACT299SC
74ACT299SCX	74ACT299SCX
74ACT299MTCX	74ACT299MTCX

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74AC299 • 74ACT299 8-Input Universal Shift/Storage Register 74AC299 • 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins The AC/ACT299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible hold store , shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0, Q7 to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register. s ICC and IOZ reduced by 50% s Common parallel I/O for reduced pin count s Additional serial inputs and outputs for expansion s Four operating modes shift left, shift right, load and store s 3-STATE outputs for bus-oriented applications s Outputs source/sink 24 mA s ACT299 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC299SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body 74AC299SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74AC299MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74AC299PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACT299SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body 74ACT299MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT299PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names CP DS0 DS7 S0, S1 MR OE1, OE2 Q0, Q7 Description Clock Pulse Input Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset 3-STATE Output Enable Inputs Parallel Data Inputs or 3-STATE Parallel Outputs Serial Outputs is a trademark of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS009893 74AC299 • 74ACT299 Logic Symbols IEEE/IEC Truth Table Inputs Response MR S1 S0 CP X H L H X Asynchronous Reset = LOW Parallel Load I/On Qn Shift Right DS0 Q0, Q0 Q1, etc. Shift Left, DS7 Q7, Q7 Q6, etc. H L X Hold H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Transition Functional Description The AC/ACT299 contains eight edge-triggered D-type flipflops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Truth Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. 74AC299 • 74ACT299 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74AC299 • 74ACT299 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC +0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC +0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current Per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC +0.5V −20 mA +20 mA −0.5V to VCC +0.5V ± 50 mA ± 50 mA −65°C to +150°C 140°C Recommended Operating Conditions Supply Voltage VCC Unless Otherwise Specified 2.0V to 6.0V

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74AC299
• 74ACT299 8-Input Universal Shift/Storage Register
74AC299
• 74ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins

The AC/ACT299 is an 8-bit universal shift/storage register with 3-STATE outputs. Four modes of operation are possible hold store , shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0, Q7 to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register.
s ICC and IOZ reduced by 50% s Common parallel I/O for reduced pin count s Additional serial inputs and outputs for expansion s Four operating modes shift left, shift right, load
and store s 3-STATE outputs for bus-oriented applications s Outputs source/sink 24 mA s ACT299 has TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74AC299SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
74AC299SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74AC299MTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74AC299PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACT299SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
74ACT299MTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACT299PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names CP DS0 DS7 S0, S1 MR OE1, OE2

Q0, Q7

Description Clock Pulse Input Serial Data Input for Right Shift Serial Data Input for Left Shift Mode Select Inputs Asynchronous Master Reset 3-STATE Output Enable Inputs Parallel Data Inputs or
3-STATE Parallel Outputs Serial Outputs
is a trademark of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS009893
74AC299
• 74ACT299

Logic Symbols

IEEE/IEC

Truth Table

Inputs

Response

MR S1 S0 CP

X H L H

X Asynchronous Reset = LOW

Parallel Load I/On Qn Shift Right DS0 Q0, Q0 Q1, etc. Shift Left, DS7 Q7, Q7 Q6, etc.

H L X Hold

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Transition

Functional Description

The AC/ACT299 contains eight edge-triggered D-type flipflops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Truth Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words.

A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed.

A HIGH signal on either OE1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation.
74AC299
• 74ACT299

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74AC299
• 74ACT299

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC +0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC +0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current Per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC +0.5V
−20 mA +20 mA −0.5V to VCC +0.5V ± 50 mA
± 50 mA −65°C to +150°C
140°C

Recommended Operating Conditions

Supply Voltage VCC Unless Otherwise Specified
2.0V to 6.0V

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Datasheet ID: 74ACT299MTC 513172