74ACT18823SSCX

74ACT18823SSCX Datasheet

74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
74ACT18823SSCX	74ACT18823SSCX (pdf)

Related Parts	Information
74ACT18823MTD	74ACT18823MTD
74ACT18823MTDX	74ACT18823MTDX
74ACT18823SSC	74ACT18823SSC

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74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs 74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs The ACT18823 contains eighteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock CP , Clear CLR , Clock Enable EN and Output Enable OE are common to each byte and can be shorted together for full 18-bit operation. s Broadside pinout allows for easy board layout s Separate control logic for each byte s Extra data width for wider address/data paths or buses carrying parity s Outputs source/sink 24 mA s TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74ACT18823SSC MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide 74ACT18823MTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names OEn CLRn ENn CPn Description Output Enable Input Active LOW Clear Active LOW Clock Enable Active LOW Clock Pulse Input Inputs Outputs FACT is a trademark of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS500294 74ACT18823 Functional Description The ACT18823 consists of eighteen D-type edge-triggered flip-flops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. The buffered clock CPn and buffered Output Enable OEn are common to all flip-flops within that byte. The flip-flops will store the state of their individual D inputs that meet set-up and hold time requirements on the LOW-to-HIGH CPn transition. With OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the impedance state. Operation of the OEn input does not affect the state of the flip-flops. In addition to the Clock and Output Enable pins, there are Clear CLRn and Clock Enable ENn pins. These devices are ideal for parity bus interfacing in high performance systems. When CLRn is LOW and OEn is LOW, the outputs are LOW. When CLRn is HIGH, data can be entered into the flip-flops. When ENn is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the ENn is HIGH, the outputs do not change state, regardless of the data or clock input transitions. Logic Diagrams Function Table Note 1 Inputs OE CLR EN CP H X L H X L Internal Output Function Z High Z Z High Z HL XXX Z Clear L LXXX L Clear H X NC Z Hold L HHX X NC Hold Z Load Z Load L Load H Load H= HIGH Voltage Level L= LOW Voltage Level X= Immaterial High Impedance = LOW-to-HIGH Transition NC= No Change Note 1 The table represents the logic for one byte. The two bytes are independent of each other and function identically. Byte 1 0:8 Byte 2 9:17 74ACT18823 Absolute Maximum Ratings Note 2

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74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs
74ACT18823 18-Bit D-Type Flip-Flop with 3-STATE Outputs

The ACT18823 contains eighteen non-inverting D-type flipflops with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. A buffered clock CP , Clear CLR , Clock Enable EN and Output Enable OE are common to each byte and can be shorted together for full 18-bit operation.
s Broadside pinout allows for easy board layout s Separate control logic for each byte s Extra data width for wider address/data paths or buses
carrying parity s Outputs source/sink 24 mA s TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74ACT18823SSC

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
74ACT18823MTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Connection Diagram

Pin Descriptions

Pin Names

OEn CLRn ENn CPn

Description Output Enable Input Active LOW Clear Active LOW Clock Enable Active LOW Clock Pulse Input Inputs Outputs

FACT is a trademark of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS500294
74ACT18823

Functional Description

The ACT18823 consists of eighteen D-type edge-triggered flip-flops. These have 3-STATE outputs for bus systems organized with inputs and outputs on opposite sides. The device is byte controlled with each byte functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. The buffered clock CPn and buffered Output Enable OEn are common to all flip-flops within that byte. The flip-flops will store the state of their individual D inputs that meet set-up and hold time requirements on the LOW-to-HIGH CPn transition. With OEn LOW, the contents of the flip-flops are available at the outputs. When OEn is HIGH, the outputs go to the impedance state. Operation of the OEn input does not affect the state of the flip-flops. In addition to the Clock and Output Enable pins, there are Clear CLRn and Clock Enable ENn pins. These devices are ideal for parity bus interfacing in high performance systems.

When CLRn is LOW and OEn is LOW, the outputs are LOW. When CLRn is HIGH, data can be entered into the flip-flops. When ENn is LOW, data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition. When the ENn is HIGH, the outputs do not change state, regardless of the data or clock input transitions.

Logic Diagrams

Function Table

Note 1

Inputs OE CLR EN CP

H X L H X L

Internal Output

Function

Z High Z

Z High Z

HL XXX

Z Clear

L LXXX

L Clear

H X NC

Z Hold

L HHX X

NC Hold

Z Load

Z Load

L Load

H Load

H= HIGH Voltage Level L= LOW Voltage Level X= Immaterial

High Impedance = LOW-to-HIGH Transition NC= No Change

Note 1 The table represents the logic for one byte. The two bytes are independent of each other and function identically.

Byte 1 0:8

Byte 2 9:17
74ACT18823

Absolute Maximum Ratings Note 2

More datasheets: 9230-92 | 9230-88 | 9230-80 | 9230-76 | 9230-68 | 9230-64 | 9230-60 | 9230-56 | 9230-52 | 17000179A

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Datasheet ID: 74ACT18823SSCX 513165