74ACTQ646SCX

74ACTQ646SCX Datasheet

74ACQ646<br>• 74ACTQ646 Quiet Octal Transceiver/Register with 3-STATE Outputs

Part	Datasheet
74ACTQ646SCX	74ACTQ646SCX (pdf)

Related Parts	Information
74ACQ646SC	74ACQ646SC
74ACTQ646SC	74ACTQ646SC

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74ACQ646 • 74ACTQ646 Quiet Octal Transceiver/Register with 3-STATE Outputs 74ACQ646 • 74ACTQ646 Quiet Octal Transceiver/Register with 3-STATE Outputs The ACQ/ACTQ646 consist of registered bus transceiver circuits, with outputs, D-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin CPAB or CPBA . The four fundamental handling functions available are illustrated in Figure 1, Figure 2, Figure 3 and Figure The ACQ/ACTQ utilizes Fairchild Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet features output control and undershoot corrector in addition to a split ground bus for superior performance. s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Independent registers for A and B busses s Multiplexed real-time and stored data transfers s 300 mil slim dual-in-line package s Outputs source/sink 24 mA s Faster prop delays than the standard AC/ACT646 Ordering Code: Order Number Package Number Package Description 74ACQ646SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACQ464ASPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACTQ646SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACTQ464ASPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names CPAB, CPBA SAB, SBA G DIR Descriptions Data Register A Inputs Data Register A Outputs Data Register B Inputs Data Register B Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Input Direction Control Input Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation 2000 Fairchild Semiconductor Corporation DS010635 74ACQ646 • 74ACTQ646 Logic Symbols IEEE/IEC Function Table Inputs Data I/O Note 1 G DIR CPAB CPBA SAB SBA Function H or L H or L H or L X X H or L X H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Transition Isolation X Input Clock An Data into A Register Clock Bn Data into B Register An to Time Transparent Mode X Input Output Clock An Data into A Register A Register to Bn Stored Mode Clock An Data into A Register and Output to Bn Bn to Time Transparent Mode L Output Input Clock Bn Data into B Register B Register to An Stored Mode Clock Bn Data into B Register and Output to An Note 1 The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. 74ACQ646 • 74ACTQ646 Real Time Transfer A-Bus to B-Bus FIGURE Storage from Bus to Register FIGURE Logic Diagram Real Time Transfer B-Bus to A-Bus FIGURE Transfer from Register to Bus FIGURE

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74ACQ646
• 74ACTQ646 Quiet Octal Transceiver/Register with 3-STATE Outputs
74ACQ646
• 74ACTQ646

Quiet Octal Transceiver/Register with 3-STATE Outputs

The ACQ/ACTQ646 consist of registered bus transceiver circuits, with outputs, D-type flip-flops, and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin CPAB or CPBA . The four fundamental handling functions available are illustrated in Figure 1, Figure 2, Figure 3 and Figure

The ACQ/ACTQ utilizes Fairchild Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet features output control and undershoot corrector in addition to a split ground bus for superior performance.
s Guaranteed simultaneous switching noise level and dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance s Independent registers for A and B busses s Multiplexed real-time and stored data transfers s 300 mil slim dual-in-line package s Outputs source/sink 24 mA s Faster prop delays than the standard AC/ACT646
Ordering Code:

Order Number Package Number

Package Description
74ACQ646SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACQ464ASPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACTQ646SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACTQ464ASPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

CPAB, CPBA SAB, SBA G DIR

Descriptions Data Register A Inputs Data Register A Outputs Data Register B Inputs Data Register B Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Input Direction Control Input

Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation
2000 Fairchild Semiconductor Corporation DS010635
74ACQ646
• 74ACTQ646

Logic Symbols

IEEE/IEC

Function Table

Inputs

Data I/O Note 1

G DIR CPAB CPBA SAB SBA

Function

H or L H or L

H or L X

X H or L X

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Transition

Isolation

X Input Clock An Data into A Register

Clock Bn Data into B Register

An to Time Transparent Mode

X Input Output Clock An Data into A Register

A Register to Bn Stored Mode

Clock An Data into A Register and Output to Bn

Bn to Time Transparent Mode

L Output Input Clock Bn Data into B Register

B Register to An Stored Mode

Clock Bn Data into B Register and Output to An

Note 1 The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.
74ACQ646
• 74ACTQ646

Real Time Transfer A-Bus to B-Bus

FIGURE Storage from Bus to Register

FIGURE

Logic Diagram

Real Time Transfer B-Bus to A-Bus

FIGURE Transfer from Register to Bus

FIGURE

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Datasheet ID: 74ACTQ646SCX 513153