74ACQ544SC

74ACQ544SC Datasheet

74ACQ544<br>• 74ACTQ544 Quiet Octal Registered Transceiver with 3-STATE Outputs

Part	Datasheet
74ACQ544SC	74ACQ544SC (pdf)

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74ACQ544 • 74ACTQ544 Quiet Octal Registered Transceiver with 3-STATE Outputs 74ACQ544 • 74ACTQ544 Quiet Octal Registered Transceiver with 3-STATE Outputs The ACQ/ACTQ544 is an inverting octal transceiver containing two sets of D-type registers for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow. The 544 inverts data in both directions. The ACQ/ACTQ utilizes Fairchild FACT Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features output control and undershoot corrector in addition to a split ground bus for superior performance. s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s 8-bit inverting octal latched transceiver s Separate controls for data flow in each direction s Back-to-back registers for storage s Outputs source/sink 24 mA Ordering Code: Order Number Package Number Package Description 74ACQ544SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACQ544SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACTQ544SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACTQ544SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names OEAB OEBA CEAB CEBA LEAB LEBA A0 A-to-B Output Enable Input Active LOW B-to-A Output Enable Input Active LOW A-to-B Enable Input Active LOW B-to-A Enable Input Active LOW A-to-B Latch Enable Input Active LOW B-to-A Latch Enable Input Active LOW A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B 3-STATE Outputs Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS010685 74ACQ544 • 74ACTQ544 Logic Symbols IEEE/IEC Logic Diagram Functional Description The ACQ/ACTQ544 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable CEAB input must be LOW in order to enter data from A0 or take data from B0 as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable LEAB input makes the A-to-B latches transparent a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA inputs. Data I/O Control Table Inputs Latch Output CEAB LEAB OEAB Status Buffers Latched High Z Latched Transparent High Z Driving H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown B-to-A flow control is the same, except using CEBA, LEBA and OEBA Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACQ544 • 74ACTQ544 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-up Source or Sink Current Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V

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74ACQ544
• 74ACTQ544 Quiet Octal Registered Transceiver with 3-STATE Outputs
74ACQ544
• 74ACTQ544

Quiet Octal Registered Transceiver with 3-STATE Outputs

The ACQ/ACTQ544 is an inverting octal transceiver containing two sets of D-type registers for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow. The 544 inverts data in both directions.

The ACQ/ACTQ utilizes Fairchild FACT Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features output control and undershoot corrector in addition to a split ground bus for superior performance.
s Guaranteed simultaneous switching noise level and dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance s 8-bit inverting octal latched transceiver s Separate controls for data flow in each direction s Back-to-back registers for storage s Outputs source/sink 24 mA
Ordering Code:

Order Number Package Number

Package Description
74ACQ544SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACQ544SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACTQ544SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACTQ544SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

OEAB OEBA CEAB CEBA LEAB LEBA A0

A-to-B Output Enable Input Active LOW B-to-A Output Enable Input Active LOW A-to-B Enable Input Active LOW B-to-A Enable Input Active LOW A-to-B Latch Enable Input Active LOW B-to-A Latch Enable Input Active LOW A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B 3-STATE Outputs

Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation.
2000 Fairchild Semiconductor Corporation DS010685
74ACQ544
• 74ACTQ544

Logic Symbols

IEEE/IEC

Logic Diagram

Functional Description

The ACQ/ACTQ544 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable CEAB input must be LOW in order to enter data from A0 or take data from B0 as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable LEAB input makes the A-to-B latches transparent a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA inputs.

Data I/O Control Table

Inputs

Latch

Output

CEAB LEAB OEAB

Status

Buffers

Latched

High Z

Latched

Transparent

High Z

Driving

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial A-to-B data flow shown B-to-A flow control is the same, except using

CEBA, LEBA and OEBA

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACQ544
• 74ACTQ544

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-up Source or

Sink Current

Junction Temperature TJ PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V

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Datasheet ID: 74ACQ544SC 513151