74ACQ543SC
74ACQ543SC Datasheet
74ACQ543• 74ACTQ543 Quiet Octal Registered Transceiver with 3-STATE Outputs
| Part | Datasheet |
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74ACQ543SC |
74ACQ543SC (pdf) |
| Related Parts | Information |
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74ACQ543SCX |
74ACQ543SCX |
74ACQ543SPC |
74ACQ543SPC |
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| 74ACQ543• 74ACTQ543 Quiet Octal Registered Transceiver with 3-STATE Outputs 74ACQ543• 74ACTQ543 Quiet Octal Registered Transceiver with 3-STATE Outputs The ACQ/ACTQ543 is a non-inverting octal transceiver containing two sets of D-type registers for temporary storage of data flowing in either direction. Separate Latch Enable and Output Enable inputs are provided for each register to permit independent input and output control in either direction of data flow. The ACQ/ACTQ utilizes Fairchild Quiet technology to guarantee quiet output switching and improved dynamic threshold performance FACT Quiet features output control and undershoot corrector in addition to a split ground bus for superior performance. s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s 8-bit octal latched transceiver s Separate controls for data flow in each direction s Back-to-back registers for storage s Outputs source/sink 24 mA s 300 mil slim PDIP/SOIC Ordering Code: Order Number Package Number Package Description 74ACQ543SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACQ543SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACTQ543SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACTQ543QSC MQA24 24-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide 74ACTQ543SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the order code. Connection Diagram Pin Descriptions Pin Names OEAB OEBA CEAB CEBA LEAB LEBA A-to-B Output Enable Input Active LOW B-to-A Output Enable Input Active LOW A-to-B Enable Input Active LOW B-to-A Enable Input Active LOW A-to-B Latch Enable Input Active LOW B-to-A Latch Enable Input Active LOW A-to-B Data Inputs or B-to-A 3-STATE Outputs B-to-A Data Inputs or A-to-B 3-STATE Outputs Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS010154 74ACQ543• 74ACTQ543 Logic Symbols IEEE/IEC Logic Diagram Functional Description The ACQ/ACTQ543 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from A to B, for example, the A-to-B Enable CEAB input must be LOW in order to enter data from or take data from as indicated in the Data I/O Control Table. With CEAB LOW, a LOW signal on the A-to-B Latch Enable LEAB input makes the A-to-B latches transparent a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the 3-STATE B output buffers are active and reflect the data present at the output of the A latches. Control of data flow from B to A is similar, but using the CEBA, LEBA and OEBA inputs Data I/O Control Table Inputs Latch Status Output Buffers CEAB LEAB OEAB Latched High Z Latched Transparent High Z Driving |
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