74ACTQ374PC

74ACTQ374PC Datasheet

74ACQ374<br>• 74ACTQ374 Quiet Octal D-Type Flip-Flop with 3-STATE Outputs

Part	Datasheet
74ACTQ374PC	74ACTQ374PC (pdf)

PDF Datasheet Preview
74ACQ374 • 74ACTQ374 Quiet Octal D-Type Flip-Flop with 3-STATE Outputs 74ACQ374 • 74ACTQ374 Quiet Octal D-Type Flip-Flop with 3-STATE Outputs The ACQ/ACTQ374 is a high-speed, low-power octal Dtype flip-flop featuring separate D-type inputs for each flipflop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable OE are common to all flip-flops. The ACQ/ACTQ374 utilizes FACT Quiet technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features output control and undershoot corrector in addition to a split ground bus for superior performance. s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s Buffered positive edge-triggered clock s 3-STATE outputs drive bus lines or buffer memory address registers s Outputs source/sink 24 mA s Faster prop delays than the standard AC/ACT374 Ordering Code: Order Number Package Number Package Description 74ACQ374SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body 74ACQ374SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACQ374PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACTQ374SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body 74ACTQ374SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACTQ374QSC MQA20 20-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide 74ACTQ374PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Pin Descriptions Pin Names CP OE Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS010238 74ACQ374 • 74ACTQ374 Logic Symbols IEEE/IEC Logic Diagram Functional Description The ACQ/ACTQ374 consists of eight edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Truth Table Inputs H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = High Impedance = LOW-to-HIGH Transition Outputs On H L Z Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACQ374 • 74ACTQ374 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-Up Source or Sink Current Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C ±300 mA 140°C Recommended Operating Conditions Supply Voltage VCC ACQ 2.0V to 6.0V ACTQ 4.5V to 5.5V Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate 0V to VCC 0V to VCC −40°C to +85°C ACQ Devices

PDF Datasheet Preview

74ACQ374
• 74ACTQ374 Quiet Octal D-Type Flip-Flop with 3-STATE Outputs
74ACQ374
• 74ACTQ374

Quiet Octal D-Type Flip-Flop with 3-STATE Outputs

The ACQ/ACTQ374 is a high-speed, low-power octal Dtype flip-flop featuring separate D-type inputs for each flipflop and 3-STATE outputs for bus-oriented applications. A buffered Clock CP and Output Enable OE are common to all flip-flops.

The ACQ/ACTQ374 utilizes FACT Quiet technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series features output control and undershoot corrector in addition to a split ground bus for superior performance.
s ICC and IOZ reduced by 50% s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s Buffered positive edge-triggered clock s 3-STATE outputs drive bus lines or buffer memory
address registers s Outputs source/sink 24 mA s Faster prop delays than the standard AC/ACT374
Ordering Code:

Order Number Package Number

Package Description
74ACQ374SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
74ACQ374SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ACQ374PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACTQ374SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
74ACTQ374SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ACTQ374QSC

MQA20
20-Lead Quarter Size Outline Package QSOP , JEDEC MO-137, Wide
74ACTQ374PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names CP OE

Description Data Inputs Clock Pulse Input 3-STATE Output Enable Input 3-STATE Outputs

Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS010238
74ACQ374
• 74ACTQ374

Logic Symbols

IEEE/IEC

Logic Diagram

Functional Description

The ACQ/ACTQ374 consists of eight edge-triggered flipflops with individual D-type inputs and 3-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock CP transition. With the Output Enable OE LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops.

Truth Table

Inputs

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
= High Impedance = LOW-to-HIGH Transition

Outputs On H L Z

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74ACQ374
• 74ACTQ374

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-Up Source or Sink Current

Junction Temperature TJ PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
±50 mA
±50 mA −65°C to +150°C
±300 mA
140°C

Recommended Operating Conditions

Supply Voltage VCC ACQ
2.0V to 6.0V

ACTQ
4.5V to 5.5V

Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate
0V to VCC 0V to VCC −40°C to +85°C

ACQ Devices

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 74ACTQ374PC Datasheet file may be downloaded here without warranties.

Datasheet ID: 74ACTQ374PC 513112