74AC646SPC

74AC646SPC Datasheet

74AC646<br>• 74ACT646 Octal Transceiver/Register with 3-STATE Outputs

Part	Datasheet
74AC646SPC	74AC646SPC (pdf)

Related Parts	Information
74AC646SC	74AC646SC
74ACT646SC	74ACT646SC
74ACT646SCX	74ACT646SCX
74AC646SCX	74AC646SCX

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74AC646 • 74ACT646 Octal Transceiver/Register with 3-STATE Outputs 74AC646 • 74ACT646 Octal Transceiver/Register with 3-STATE Outputs The AC/ACT646 consist of registered bus transceiver circuits, with outputs, D-type flip-flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin CPAB or CPBA . The four fundamental data handling functions available are illustrated in Figures 1, 2, 3, and Figure s Independent registers for A and B buses s Multiplexed real-time and stored data transfers s 3-STATE outputs s 300 mil dual-in-line package s Outputs source/sink 24 mA s ACT646 has TTL compatible inputs Ordering Code: Order Number Package Number Package Description 74AC646SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74AC646SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACT646SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACT646SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names CPAB, CPBA SAB, SBA G DIR Description Data Register A Inputs Data Register A Outputs Data Register B Inputs Data Register B Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Input Direction Control Input is a trademark of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS010132 74AC646 • 74ACT646 Function Table Inputs Data I/O Note 1 G DIR CPAB CPBA SAB SBA Function X H or L H or L X Isolation Input Clock An Data into A Register Clock Bn Data into B Register An to Time Transparent Mode Input Output Clock An Data into A Register H or L X A Register to Bn Stored Mode Clock An Data into A Register and Output to Bn Bn to An Time Transparent Mode L Output Input Clock Bn Data into B Register X H or L X B Register to An Stored Mode Clock Bn Data into B Register and Output to An H = HIGH Voltage Level L = LOW Voltage Level = Immaterial = LOW-to-HIGH Transition Note 1 The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs. Real Time Transfer A-Bus to B-Bus Real Time Transfer B-Bus to A-Bus FIGURE Storage from Bus to Register FIGURE FIGURE Transfer from Register to Bus FIGURE 74AC646 • 74ACT646 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74AC646 • 74ACT646

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74AC646
• 74ACT646 Octal Transceiver/Register with 3-STATE Outputs
74AC646
• 74ACT646 Octal Transceiver/Register with 3-STATE Outputs

The AC/ACT646 consist of registered bus transceiver circuits, with outputs, D-type flip-flops and control circuitry providing multiplexed transmission of data directly from the input bus or from the internal storage registers. Data on the A or B bus will be loaded into the respective registers on the LOW-to-HIGH transition of the appropriate clock pin CPAB or CPBA . The four fundamental data handling functions available are illustrated in Figures 1, 2, 3, and Figure
s Independent registers for A and B buses s Multiplexed real-time and stored data transfers s 3-STATE outputs s 300 mil dual-in-line package s Outputs source/sink 24 mA s ACT646 has TTL compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74AC646SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74AC646SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACT646SC

M24B
24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
74ACT646SPC

N24C
24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names

CPAB, CPBA SAB, SBA G DIR

Description Data Register A Inputs Data Register A Outputs Data Register B Inputs Data Register B Outputs Clock Pulse Inputs Transmit/Receive Inputs Output Enable Input Direction Control Input
is a trademark of Fairchild Semiconductor Corporation.
2000 Fairchild Semiconductor Corporation DS010132
74AC646
• 74ACT646

Function Table

Inputs

Data I/O Note 1

G DIR CPAB CPBA SAB SBA

Function

X H or L H or L X

Isolation

Input Clock An Data into A Register

Clock Bn Data into B Register

An to Time Transparent Mode

Input Output Clock An Data into A Register

H or L X

A Register to Bn Stored Mode Clock An Data into A Register and Output to Bn

Bn to An Time Transparent Mode

L Output Input Clock Bn Data into B Register

X H or L X

B Register to An Stored Mode Clock Bn Data into B Register and Output to An

H = HIGH Voltage Level L = LOW Voltage Level
= Immaterial = LOW-to-HIGH Transition

Note 1 The data output functions may be enabled or disabled by various signals at the G and DIR inputs. Data input functions are always enabled i.e., data at the bus pins will be stored on every LOW-to-HIGH transition of the appropriate clock inputs.

Real Time Transfer A-Bus to B-Bus

Real Time Transfer B-Bus to A-Bus

FIGURE Storage from Bus to Register

FIGURE

FIGURE Transfer from Register to Bus

FIGURE
74AC646
• 74ACT646

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74AC646
• 74ACT646

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Datasheet ID: 74AC646SPC 513107