74ACT573SCX

74ACT573SCX Datasheet

74AC573, 74ACT573 Octal Latch with 3-STATE Outputs

Part	Datasheet
74ACT573SCX	74ACT573SCX (pdf)

Related Parts	Information
74ACT573SJX	74ACT573SJX
74ACT573MTCX	74ACT573MTCX
74ACT573MTC	74ACT573MTC
74ACT573SJ	74ACT573SJ
74ACT573SC	74ACT573SC
74ACT573PC	74ACT573PC

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74AC573, 74ACT573 Octal Latch with 3-STATE Outputs January 2008 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs • ICC and IOZ reduced by 50% • Inputs and outputs on opposite sides of package allowing easy interface with microprocessors • Useful as input or output port for microprocessors • Functionally identical to 74AC373 and 74ACT373 • 3-STATE outputs for bus interfacing • Outputs source/sink 24mA • 74ACT573 has TTL-compatible inputs The 74AC573 and 74ACT573 are high-speed octal latches with buffered common Latch Enable LE and buffered common Output Enable OE inputs. The 74AC573 and 74ACT573 are functionally identical to the 74AC373 and 74ACT373 but with inputs and outputs on opposite sides. Ordering Information Order Number 74AC573SC 74AC573SJ 74AC573MTC 74ACT573SC 74ACT573SJ 74ACT573MTC 74ACT573PC Package Number M20B M20D MTC20 M20B M20D MTC20 N20A Package Description 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number. All packages are lead free per JEDEC J-STD-020B standard. 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs Connection Diagram Logic Symbols IEEE/IEC Pin Description Pin Names LE OE Description Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs Functional Description The 74AC573 and 74ACT573 contain eight D-type latches with 3-STATE output buffers. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the information that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Table Inputs Outputs On H L O0 Z H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable 1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 1988 Fairchild Semiconductor Corporation 74AC573, 74ACT573 Octal Latch with 3-STATE Outputs Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Parameter VCC IIK VI IOK VO IO ICC or IGND TSTG TJ Supply Voltage DC Input Diode Current VI = VI = VCC + DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature Rating to +7.0V +20mA to VCC + 0.5V +20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VCC VI VO TA / Parameter Supply Voltage AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V Rating 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC to +85°C 125mV/ns

PDF Datasheet Preview

74AC573, 74ACT573 Octal Latch with 3-STATE Outputs

January 2008
74AC573, 74ACT573 Octal Latch with 3-STATE Outputs
• ICC and IOZ reduced by 50%
• Inputs and outputs on opposite sides of package
allowing easy interface with microprocessors
• Useful as input or output port for microprocessors
• Functionally identical to 74AC373 and 74ACT373
• 3-STATE outputs for bus interfacing
• Outputs source/sink 24mA
• 74ACT573 has TTL-compatible inputs

The 74AC573 and 74ACT573 are high-speed octal latches with buffered common Latch Enable LE and buffered common Output Enable OE inputs.

The 74AC573 and 74ACT573 are functionally identical to the 74AC373 and 74ACT373 but with inputs and outputs on opposite sides.
Ordering Information

Order Number 74AC573SC
74AC573SJ 74AC573MTC
74ACT573SC
74ACT573SJ 74ACT573MTC
74ACT573PC

Package Number

M20B

M20D MTC20

M20B

M20D MTC20

N20A

Package Description
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC J-STD-020B standard.
74AC573, 74ACT573 Octal Latch with 3-STATE Outputs

Connection Diagram

Logic Symbols

IEEE/IEC

Pin Description

Pin Names LE OE

Description Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs

Functional Description

The 74AC573 and 74ACT573 contain eight D-type latches with 3-STATE output buffers. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the information that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.

Truth Table

Inputs

Outputs On H L O0 Z

H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable
1988 Fairchild Semiconductor Corporation
74AC573, 74ACT573 Octal Latch with 3-STATE Outputs

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
1988 Fairchild Semiconductor Corporation
74AC573, 74ACT573 Octal Latch with 3-STATE Outputs

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.

Parameter

VCC IIK

VI IOK

VO IO ICC or IGND TSTG TJ

Supply Voltage DC Input Diode Current

VI = VI = VCC + DC Input Voltage DC Output Diode Current VO = VO = VCC + 0.5V DC Output Voltage DC Output Source or Sink Current DC VCC or Ground Current per Output Pin Storage Temperature Junction Temperature

Rating to +7.0V
+20mA to VCC + 0.5V
+20mA to VCC + 0.5V ±50mA ±50mA to +150°C 140°C

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings.

Symbol VCC

VI VO TA /

Parameter Supply Voltage

AC ACT Input Voltage Output Voltage Operating Temperature Minimum Input Edge Rate, AC Devices VIN from 30% to 70% of VCC, VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices VIN from 0.8V to 2.0V, VCC 4.5V, 5.5V

Rating
2.0V to 6.0V 4.5V to 5.5V
0V to VCC 0V to VCC to +85°C 125mV/ns

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Datasheet ID: 74ACT573SCX 513104