74AC573SJX

74AC573SJX Datasheet

74AC573<br>• 74ACT573 Octal Latch with 3-STATE Outputs

Part	Datasheet
74AC573SJX	74AC573SJX (pdf)

Related Parts	Information
74AC573PC	74AC573PC
74AC573MTCX	74AC573MTCX
74AC573MTC	74AC573MTC
74AC573SCX	74AC573SCX
74AC573SC	74AC573SC
74AC573SJ	74AC573SJ

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74AC573 • 74ACT573 Octal Latch with 3-STATE Outputs 74AC573 • 74ACT573 Octal Latch with 3-STATE Outputs The 74AC573 and 74ACT573 are high-speed octal latches with buffered common Latch Enable LE and buffered common Output Enable OE inputs. The 74AC573 and 74ACT573 are functionally identical to the 74AC373 and 74ACT373 but with inputs and outputs on opposite sides. s ICC and IOZ reduced by 50% s Inputs and outputs on opposite sides of package allow- ing easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to 74AC373 and 74ACT373 s 3-STATE outputs for bus interfacing s Outputs source/sink 24 mA s 74ACT573 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC573SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS--013, Wide Body 74AC573SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74AC573MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74AC573PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACT573SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS--013, Wide Body 74ACT573SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACT573MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT573PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names Data Inputs Latch Enable Input 3-STATE Output Enable Input 3-STATE Latch Outputs FACT is a trademark of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS009973 74AC573 • 74ACT573 Functional Description The 74AC573 and 74ACT573 contain eight D-type latches with 3-STATE output buffers. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the information that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Table Inputs H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Outputs On H L O0 Z Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74AC573 • 74ACT573 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ±50 mA ±50 mA −65°C to +150°C 140°C Recommended Operating Conditions Supply Voltage VCC AC 2.0V to 6.0V 4.5V to 5.5V Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate 0V to VCC 0V to VCC −40°C to +85°C AC Devices

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74AC573
• 74ACT573 Octal Latch with 3-STATE Outputs
74AC573
• 74ACT573 Octal Latch with 3-STATE Outputs

The 74AC573 and 74ACT573 are high-speed octal latches with buffered common Latch Enable LE and buffered common Output Enable OE inputs.

The 74AC573 and 74ACT573 are functionally identical to the 74AC373 and 74ACT373 but with inputs and outputs on opposite sides.
s ICC and IOZ reduced by 50% s Inputs and outputs on opposite sides of package allow-
ing easy interface with microprocessors s Useful as input or output port for microprocessors s Functionally identical to 74AC373 and 74ACT373 s 3-STATE outputs for bus interfacing s Outputs source/sink 24 mA s 74ACT573 has TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74AC573SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS--013, Wide Body
74AC573SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74AC573MTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74AC573PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACT573SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS--013, Wide Body
74ACT573SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ACT573MTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACT573PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names

Data Inputs Latch Enable Input
3-STATE Output Enable Input
3-STATE Latch Outputs

FACT is a trademark of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS009973
74AC573
• 74ACT573

Functional Description

The 74AC573 and 74ACT573 contain eight D-type latches with 3-STATE output buffers. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW the latches store the information that was
present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE buffers are controlled by the Output Enable OE input. When OE is LOW, the buffers are enabled. When OE is HIGH the buffers are in the high impedance mode but this does not interfere with entering new data into the latches.

Truth Table

Inputs

H = HIGH Voltage L = LOW Voltage Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable

Outputs On H L O0 Z

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74AC573
• 74ACT573

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ

PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
±50 mA
±50 mA −65°C to +150°C
140°C

Recommended Operating Conditions

Supply Voltage VCC AC
2.0V to 6.0V
4.5V to 5.5V

Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate
0V to VCC 0V to VCC −40°C to +85°C

AC Devices

More datasheets: RSN116140 | BMA220-SHUTL | BMA220 | F0431A | F0432A | F0433A | F0434A | 74AC573PC | 74AC573MTCX | 74AC573MTC

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Datasheet ID: 74AC573SJX 513103