74ACT373MSA

74ACT373MSA Datasheet

74AC373<br>• 74ACT373 Octal Transparent Latch with 3-STATE Outputs

Part	Datasheet
74ACT373MSA	74ACT373MSA (pdf)

Related Parts	Information
74ACT373SCX	74ACT373SCX
74ACT373MSAX	74ACT373MSAX
74ACT373MTC	74ACT373MTC
74ACT373MTCX	74ACT373MTCX
74AC373MTC	74AC373MTC
74AC373SCX	74AC373SCX
74AC373SJX	74AC373SJX
74AC373MTCX	74AC373MTCX
74AC373SJ	74AC373SJ
74AC373SC	74AC373SC
74ACT373SJ	74ACT373SJ
74ACT373SJX	74ACT373SJX
74AC373PC	74AC373PC
74ACT373SC	74ACT373SC
74ACT373PC	74ACT373PC

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74AC373 • 74ACT373 Octal Transparent Latch with 3-STATE Outputs 74AC373 • 74ACT373 Octal Transparent Latch with 3-STATE Outputs The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flipflops appear transparent to the data when Latch Enable LE is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the high impedance state. s ICC and IOZ reduced by 50% s Eight latches in a single package s 3-STATE outputs for bus interfacing s Outputs source/sink 24 mA s ACT373 has TTL-compatible inputs Ordering Code: Order Number Package Number Package Description 74AC373SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body 74AC373SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74AC373MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74AC373PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide 74ACT373SC M20B 20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body 74ACT373SJ M20D 20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide 74ACT373MSA MSA20 20-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide 74ACT373MTC MTC20 20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide 74ACT373PC N20A 20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering information Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names LE OE Description Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs is a trademark of Fairchild Semiconductor Corporation. 1999 Fairchild Semiconductor Corporation DS009958 74AC373 • 74ACT373 Functional Description The AC/ACT373 contains eight D-type latches with 3STATE standard outputs. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW, the latches store the information that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable OE input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Logic Diagram Truth Table Inputs Outputs H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74AC373 • 74ACT373 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65°C to +150°C 140°C Recommended Operating Conditions Supply Voltage VCC AC 2.0V to 6.0V 4.5V to 5.5V Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate 0V to VCC 0V to VCC −40°C to +85°C AC Devices VIN from 30% to 70% of VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate 125 mV/ns ACT Devices

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74AC373
• 74ACT373 Octal Transparent Latch with 3-STATE Outputs
74AC373
• 74ACT373 Octal Transparent Latch with 3-STATE Outputs

The AC/ACT373 consists of eight latches with 3-STATE outputs for bus organized system applications. The flipflops appear transparent to the data when Latch Enable LE is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable OE is LOW. When OE is HIGH, the bus output is in the high impedance state.
s ICC and IOZ reduced by 50% s Eight latches in a single package s 3-STATE outputs for bus interfacing s Outputs source/sink 24 mA s ACT373 has TTL-compatible inputs
Ordering Code:

Order Number Package Number

Package Description
74AC373SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
74AC373SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74AC373MTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74AC373PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
74ACT373SC

M20B
20-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide Body
74ACT373SJ

M20D
20-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide
74ACT373MSA

MSA20
20-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide
74ACT373MTC

MTC20
20-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide
74ACT373PC

N20A
20-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering information

Logic Symbols

Connection Diagram

IEEE/IEC

Pin Descriptions

Pin Names LE OE

Description Data Inputs Latch Enable Input Output Enable Input 3-STATE Latch Outputs
is a trademark of Fairchild Semiconductor Corporation.
1999 Fairchild Semiconductor Corporation DS009958
74AC373
• 74ACT373

Functional Description

The AC/ACT373 contains eight D-type latches with 3STATE standard outputs. When the Latch Enable LE input is HIGH, data on the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change state each time its D-type input changes. When LE is LOW, the latches store the information that was present on the D-type inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-STATE standard outputs are controlled by the Output Enable OE input. When OE is LOW, the standard outputs are in the 2-state mode. When OE is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches.

Logic Diagram

Truth Table

Inputs

Outputs

H = HIGH Voltage Level L = LOW Voltage Level Z = High Impedance X = Immaterial O0 = Previous O0 before HIGH-to-LOW transition of Latch Enable

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
74AC373
• 74ACT373

Absolute Maximum Ratings Note 1

Supply Voltage VCC DC Input Diode Current IIK

VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source
or Sink Current IO DC VCC or Ground Current
per Output Pin ICC or IGND Storage Temperature TSTG Junction Temperature TJ

PDIP
−0.5V to +7.0V
−20 mA +20 mA −0.5V to VCC + 0.5V
−20 mA +20 mA −0.5V to VCC + 0.5V
± 50 mA
± 50 mA −65°C to +150°C
140°C

Recommended Operating Conditions

Supply Voltage VCC AC
2.0V to 6.0V
4.5V to 5.5V

Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate
0V to VCC 0V to VCC −40°C to +85°C

AC Devices

VIN from 30% to 70% of VCC 3.3V, 4.5V, 5.5V Minimum Input Edge Rate
125 mV/ns

ACT Devices

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Datasheet ID: 74ACT373MSA 513097